MC68HC708AS48 FREESCALE [Freescale Semiconductor, Inc], MC68HC708AS48 Datasheet - Page 361

• Manufacturer Part Number: MC68HC708AS48
• Description: Advance Information
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

MC68HC708AS48
MOTOROLA
—
Rev. 4.0
IMSG — Ignore Message Bit
CLKS — Clock Bit
R1 and R0 — Rate Select Bits
This bit is used to disable the receiver until a new start-of-frame (SOF)
is detected.
For J1850 bus communications to take place, the nominal BDLC
operating frequency (f
The CLKS register bit allows the user to select the frequency
(1.048576 MHz or 1 MHz) used to automatically adjust symbol timing.
These bits determine the amount by which the frequency of the MCU
CGMXCLK signal is divided to form the MUX interface clock (f
which defines the basic timing resolution of the MUX interface. They
may be written only once after reset, after which they become
read-only bits.
The nominal frequency of f
MHz for J1850 bus communications to take place. Hence, the value
programmed into these bits is dependent on the chosen MCU system
clock frequency per
1 = Disable receiver. When set, all BDLC interrupt requests will be
0 = Enable receiver. This bit is cleared automatically by the
1 = Binary frequency (1.048576 MHz) selected for f
0 = Integer frequency (1 MHz) selected for f
Byte Data Link Controller–Digital (BDLC–D)
masked (except $20 in BSVR) and the status bits will be held
in their reset state. If this bit is set while the BDLC is receiving
a message, the rest of the incoming message will be ignored.
reception of an SOF symbol or a BREAK symbol. It will then
generate interrupt requests and will allow changes of the
status register to occur. However, these interrupts may still be
masked by the interrupt enable (IE) bit.
Table
BDLC
BDLC
) must always be 1.048576 MHz or 1 MHz.
20-3.
must always be 1.048576 MHz or 1.0
Byte Data Link Controller–Digital (BDLC–D)
BDLC
BDLC CPU Interface
Advance Information
BDLC
BDLC
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