MC68HC708AS48 FREESCALE [Freescale Semiconductor, Inc], MC68HC708AS48 Datasheet - Page 366

• Manufacturer Part Number: MC68HC708AS48
• Description: Advance Information
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

Byte Data Link Controller–Digital (BDLC–D)
Advance Information
366
written to TSIFR, TMIFR1, and TMIFR0, then internally they will be
encoded as 010. However, when these bits are read back, they will
read 011.
The BDLC supports the in-frame response (IFR) feature of J1850 by
setting these bits correctly. The four types of J1850 IFR are shown in
Figure
allow multiple nodes to acknowledge receipt of the data by
responding with their personal ID or physical address in a
concatenated manner after they have seen the EOD symbol. If
transmission arbitration is lost by a node while sending its response,
it continues to transmit its ID/address until observing its unique byte
in the response stream. For VPW modulation, the first bit of the IFR is
always passive; therefore, a normalization bit (active) must be
generated by the responder and sent prior to its ID/address byte.
When there are multiple responders on the J1850 bus, only one
normalization bit is sent which assists all other transmitting nodes to
sync their responses.
Write/Read
Byte Data Link Controller–Digital (BDLC–D)
TSIFR
0
1
0
0
20-19. The purpose of the in-frame response modes is to
Table 20-4. BDLC Transmit In-Frame Response
Write/Read
TMIFR1
Control Bit Priority Encoding
X
0
1
0
Write/Read
TMIFR0
X
X
0
1
Actual
TSIFR
MC68HC708AS48
0
1
0
0
TMIFR1
Actual
0
0
1
0
MOTOROLA
—
TMIFR0
Actual
Rev. 4.0
0
0
0
1