MC68HC708AS48 FREESCALE [Freescale Semiconductor, Inc], MC68HC708AS48 Datasheet - Page 371

• Manufacturer Part Number: MC68HC708AS48
• Description: Advance Information
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

20.7.4 BDLC State Vector Register
MC68HC708AS48
MOTOROLA
—
Rev. 4.0
Address:
This register is provided to substantially decrease the CPU overhead
associated with servicing interrupts while under operation of a multiplex
protocol. It provides an index offset that is directly related to the BDLC’s
current state, which can be used with a user-supplied jump table to
rapidly enter an interrupt service routine. This eliminates the need for the
user to maintain a duplicate state machine in software.
I0, I1, I2, and I3 — Interrupt Source Bits
Reset:
BSVR
Read:
Write:
$0C
$1C
$00
$04
$08
$10
$14
$18
$20
These bits indicate the source of the interrupt request that currently is
pending. The encoding of these bits are listed in
Byte Data Link Controller–Digital (BDLC–D)
$003E
Figure 20-20. BDLC State Vector Register (BSVR)
Bit 7
I3
0
0
0
0
0
0
0
0
1
R
R
0
0
I2
0
0
0
0
1
1
1
1
0
= Reserved
Table 20-5. BDLC Interrupt Sources
I1
0
0
1
1
0
0
1
1
0
R
6
0
0
I0
0
1
0
1
0
1
0
1
0
Cyclical redundancy check (CRC) error
I3
R
BDLC Tx data register empty (TDRE)
5
0
BDLC Rx data register full (RDRF)
Symbol invalid or out of range
Received IFR byte (RXIFR)
No interrupts pending
I2
R
Loss of arbitration
4
0
Interrupt Source
Byte Data Link Controller–Digital (BDLC–D)
Received EOF
Wakeup
I1
R
3
0
I0
R
2
0
Table
BDLC CPU Interface
Advance Information
20-5.
R
1
0
0
8 (highest)
0 (lowest)
Priority
1
2
3
4
5
6
7
Bit 0
R
0
0
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