MC68HC708AS48 FREESCALE [Freescale Semiconductor, Inc], MC68HC708AS48 Datasheet - Page 389

• Manufacturer Part Number: MC68HC708AS48
• Description: Advance Information
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

21.15 BDLC Receiver VPW Symbol Timings
MC68HC708AS48
MOTOROLA
Passive logic 0
Passive logic 1
Active logic 0
Active logic 1
Start of frame (SOF)
End of data (EOD)
End of frame (EOF)
Break
1. f
2. The receiver symbol timing boundaries are subject to an uncertainty of 1 t
BDLC
= 1.048576 or 1.0 MHz, V
Figure 21-3. BDLC Variable Pulse Width Modulation (VPW) Symbol Timing
Characteristic
—
Rev. 4.0
13
1
(1) (2)
DD
11
= 5.0 V
1
SOF
14
Number
10%, V
Electrical Specifications
10
11
12
13
14
15
16
18
SS
0
EOF
16
= 0 V. See
BRK
18
Symbol
10
t
t
t
t
t
t
0
TRVP1
TRVP2
TRVA1
TRVA2
TRVA3
TRVP3
t
t
TRV4
TRV6
Figure
12
0
Min
163
163
239
280
21-3.
BDLC
34
96
96
34
EOD
15
BDLC Receiver VPW Symbol Timings
s due to sampling considerations.
Typ
128
128
200
200
280
64
64
—
Electrical Specifications
Advance Information
Max
163
163
239
239
320
96
96
—
Unit
s
s
s
s
s
s
s
s
389