PIC18F25J50 MICROCHIP [Microchip Technology], PIC18F25J50 Datasheet - Page 191
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PIC18F25J50
Manufacturer Part Number
PIC18F25J50
Description
28/44-Pin, Low-Power, High-Performance USB Microcontrollers with nanoWatt XLP Technology
Manufacturer
MICROCHIP [Microchip Technology]
Datasheet
1.PIC18F25J50.pdf
(562 pages)
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11.4
This section introduces some potential applications for
the PMP module.
FIGURE 11-27:
11.4.2
Partial multiplexing implies using more pins; however,
for a few extra pins, some extra performance can be
achieved.
memory or peripheral that is partially multiplexed with
FIGURE 11-28:
FIGURE 11-29:
2011 Microchip Technology Inc.
Application Examples
PIC18F
PIC18F
Figure 11-28
PIC18F
PARTIALLY MULTIPLEXED
MEMORY OR PERIPHERAL
PMD<7:0>
PMD<7:0>
PMD<7:0>
PMALH
PMALL
PMALL
PMWR
PMWR
PMRD
PMALL
PMRD
PMCS
PMCS
PMWR
PMCS
PMRD
MULTIPLEXED ADDRESSING APPLICATION EXAMPLE
EXAMPLE OF A PARTIALLY MULTIPLEXED ADDRESSING APPLICATION
EXAMPLE OF AN 8-BIT MULTIPLEXED ADDRESS AND DATA APPLICATION
provides an example of a
AD<7:0>
ALE
CS
RD
WR
373
373
373
Parallel Peripheral
A<15:8>
A<7:0>
D<7:0>
D<7:0>
A<7:0>
PIC18F46J50 FAMILY
11.4.1
Figure 11-27
another addressable peripheral in Full Multiplex mode.
Consequently, this mode achieves the best pin saving
from the microcontroller perspective. However, for this
configuration, there needs to be some external latches
to maintain the address.
an external latch. If the peripheral has internal latches,
as displayed in
required except for the peripheral itself.
MULTIPLEXED MEMORY OR
PERIPHERAL
A<7:0>
D<7:0>
CE
A<13:0>
D<7:0>
CE
OE
OE
demonstrates the hookup of a memory or
Figure
WR
WR
11-29, then no extra circuitry is
Address Bus
Data Bus
Control Lines
Address Bus
Data Bus
Control Lines
Address Bus
Data Bus
Control Lines
DS39931D-page 191
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