PIC18F25J50 MICROCHIP [Microchip Technology], PIC18F25J50 Datasheet - Page 273
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PIC18F25J50
Manufacturer Part Number
PIC18F25J50
Description
28/44-Pin, Low-Power, High-Performance USB Microcontrollers with nanoWatt XLP Technology
Manufacturer
MICROCHIP [Microchip Technology]
Datasheet
1.PIC18F25J50.pdf
(562 pages)
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19.3.2
When initializing the SPI, several options need to be
specified. This is done by programming the appropriate
control bits (SSPxCON1<5:0> and SSPxSTAT<7:6>).
These control bits allow the following to be specified:
• Master mode (SCKx is the clock output)
• Slave mode (SCKx is the clock input)
• Clock Polarity (Idle state of SCKx)
• Data Input Sample Phase (middle or end of data
• Clock Edge (output data on rising/falling edge of
• Clock Rate (Master mode only)
• Slave Select mode (Slave mode only)
Each MSSP module consists of a Transmit/Receive
Shift register (SSPxSR) and a Buffer register
(SSPxBUF). The SSPxSR shifts the data in and out of
the device, MSb first. The SSPxBUF holds the data that
was written to the SSPxSR until the received data is
ready. Once the 8 bits of data have been received, that
byte is moved to the SSPxBUF register. Then, the Buffer
Full (BF) detect bit (SSPxSTAT<0>) and the interrupt
flag bit, SSPxIF, are set. This double-buffering of the
received data (SSPxBUF) allows the next byte to start
reception before reading the data that was just received.
Any write to the SSPxBUF register during transmis-
sion/reception of data will be ignored and the Write
Collision Detect bit, WCOL (SSPxCON1<7>), will be set.
User software must clear the WCOL bit so that it can be
determined if the following write(s) to the SSPxBUF
register completed successfully.
EXAMPLE 19-1:
2011 Microchip Technology Inc.
LOOP
output time)
SCKx)
Note:
BTFSS
BRA
MOVF
MOVWF
MOVF
MOVWF
OPERATION
When the application software is expecting
to receive valid data, the SSPxBUF should
be read before the next byte of transfer
data is written to the SSPxBUF. Application
software should follow this process even
when the current contents of SSPxBUF
are not important.
SSP1STAT, BF
LOOP
SSP1BUF, W
RXDATA
TXDATA, W
SSP1BUF
LOADING THE SSP1BUF (SSP1SR) REGISTER
;Has data been received (transmit complete)?
;No
;WREG reg = contents of SSP1BUF
;Save in user RAM, if data is meaningful
;W reg = contents of TXDATA
;New data to xmit
PIC18F46J50 FAMILY
The Buffer Full bit, BF (SSPxSTAT<0>), indicates when
SSPxBUF has been loaded with the received data
(transmission is complete). When the SSPxBUF is read,
the BF bit is cleared. This data may be irrelevant if the
SPI is only a transmitter. Generally, the MSSP interrupt
is used to determine when the transmission/reception
has completed. If the interrupt method is not going to be
used, then software polling can be done to ensure that a
write collision does not occur.
Example 19-1
(SSPxSR) for data transmission.
The SSPxSR is not directly readable or writable and
can only be accessed by addressing the SSPxBUF
register. Additionally, the SSPxSTAT register indicates
the various status conditions.
19.3.3
The drivers for the SDOx output and SCKx clock pins
can be optionally configured as open-drain outputs.
This feature allows the voltage level on the pin to be
pulled to a higher level through an external pull-up
resistor, provided the SDOx or SCKx pin is not multi-
plexed with an ANx analog function. This allows the
output to communicate with external circuits without the
need for additional level shifters. For more information,
see
The open-drain output option is controlled by the
SPI2OD and SPI1OD bits (ODCON3<1:0>). Setting an
SPIxOD bit configures both SDOx and SCKx pins for the
corresponding open-drain operation.
Section 10.1.4 “Open-Drain
OPEN-DRAIN OUTPUT OPTION
provides the loading of the SSPxBUF
Outputs”.
DS39931D-page 273
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