PIC18F25J50 MICROCHIP [Microchip Technology], PIC18F25J50 Datasheet - Page 311

• Manufacturer Part Number: PIC18F25J50
• Description: 28/44-Pin, Low-Power, High-Performance USB Microcontrollers with nanoWatt XLP Technology
• Manufacturer: MICROCHIP [Microchip Technology]

19.5.7.2
Clock arbitration occurs when the master, during any
receive, transmit or Repeated Start/Stop condition,
deasserts the SCLx pin (SCLx allowed to float high).
When the SCLx pin is allowed to float high, the BRG is
suspended from counting until the SCLx pin is actually
FIGURE 19-20:
19.5.8
To initiate a Start condition, the user sets the Start
Enable bit, SEN (SSPxCON2<0>). If the SDAx and
SCLx pins are sampled high, the BRG is reloaded with
the contents of SSPxADD<6:0> and starts its count. If
SCLx and SDAx are both sampled high, when the Baud
Rate Generator times out (T
driven low. The action of the SDAx being driven low
while SCLx is high is the Start condition and causes the
Start bit (SSPxSTAT<3>) to be set. Following this, the
BRG is reloaded with the contents of SSPxADD<6:0>
and resumes its count. When the BRG times out
(T
automatically cleared by hardware. The BRG is sus-
pended, leaving the SDAx line held low and the Start
condition is complete.
FIGURE 19-21:
 2011 Microchip Technology Inc.
BRG
), the SEN bit (SSPxCON2<0>) will be
I
CONDITION TIMING
2
Clock Arbitration
C MASTER MODE START
SDAx
SCLx
BRG
Value
BRG
Reload
Write to SEN bit occurs here
BAUD RATE GENERATOR TIMING WITH CLOCK ARBITRATION
FIRST START BIT TIMING
03h
SDAx
SCLx
BRG
DX
), the SDAx pin is
SCLx deasserted but slave holds
SCLx low (clock arbitration)
02h
SCLx is sampled high, reload takes
place and BRG starts its count
SDAx = 1,
SCLx = 1
T
BRG
01h
Set S bit (SSPxSTAT<3>)
T
S
BRG
BRG decrements on
Q2 and Q4 cycles
00h (hold off)
PIC18F46J50 FAMILY
At completion of Start bit,
hardware clears SEN bit
sampled high. When the SCLx pin is sampled high, the
BRG is reloaded with the contents of SSPxADD<6:0>
and begins counting. This ensures that the SCLx high
time will always be at least one BRG rollover count in
the event that the clock is held low by an external
device
19.5.8.1
If the user writes the SSPxBUF when a Start sequence
is in progress, the WCOL bit is set and the contents of
the buffer are unchanged (the write does not occur).
and sets SSPxIF bit
Note:
Note:
DX – 1
Write to SSPxBUF occurs here
T
BRG
(Figure
1st bit
module is reset into its Idle state.
If, at the beginning of the Start condition, the
SDAx and SCLx pins are already sampled
low, or if during the Start condition, the SCLx
line is sampled low before the SDAx line is
driven low, a bus collision occurs, the Bus
Collision Interrupt Flag, BCLxIF, is set, the
Start condition is aborted and the I
Because queueing of events is not
allowed, writing to the lower five bits of
SSPxCON2 is disabled until the Start
condition is complete.
WCOL Status Flag
SCLx allowed to transition high
T
19-20).
BRG
03h
02h
2nd bit
DS39931D-page 311
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C