MC68HC908AP16CFA MOTOROLA [Motorola, Inc], MC68HC908AP16CFA Datasheet - Page 223
MC68HC908AP16CFA
Manufacturer Part Number
MC68HC908AP16CFA
Description
Microcontrollers
Manufacturer
MOTOROLA [Motorola, Inc]
Datasheet
1.MC68HC908AP16CFA.pdf
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13.4.3.3 Data Sampling
MC68HC908AP Family — Rev. 2.5
MOTOROLA
RT CLOCK
RT CLOCK
SAMPLES
CLOCK
RESET
STATE
RxD
RT
The receiver samples the RxD pin at the RT clock rate. The RT clock is
an internal signal with a frequency 16 times the baud rate. To adjust for
baud rate mismatch, the RT clock is resynchronized at the following
times (see
To locate the start bit, data recovery logic does an asynchronous search
for a logic 0 preceded by three logic 1s. When the falling edge of a
possible start bit occurs, the RT clock begins to count to 16.
•
•
Freescale Semiconductor, Inc.
QUALIFICATION
Figure 13-6. Receiver Data Sampling
For More Information On This Product,
START BIT
After the receiver detects a data bit change from logic 1 to logic 0
After every start bit
(after the majority of data bit samples at RT8, RT9, and RT10
returns a valid logic 1 and the majority of the next RT8, RT9, and
RT10 samples returns a valid logic 0)
Figure
Go to: www.freescale.com
13-6):
VERIFICATION
START BIT
START BIT
SAMPLING
Serial Communications Interface Module (SCI)
DATA
Functional Description
LSB
Data Sheet
223
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