MC68HC908AP16CFA MOTOROLA [Motorola, Inc], MC68HC908AP16CFA Datasheet - Page 281

• Manufacturer Part Number: MC68HC908AP16CFA
• Description: Microcontrollers
• Manufacturer: MOTOROLA [Motorola, Inc]

MC68HC908AP Family — Rev. 2.5
MOTOROLA
OR — Receiver Overrun Bit
NF — Receiver Noise Flag Bit
FE — Receiver Framing Error Bit
This clearable, read-only bit is set when software fails to read the
IRSCDR before the receive shift register receives the next character.
The OR bit generates an SCI error CPU interrupt request if the ORIE
bit in IRSCC3 is also set. The data in the shift register is lost, but the
data already in the IRSCDR is not affected. Clear the OR bit by
reading IRSCS1 with OR set and then reading the IRSCDR. Reset
clears the OR bit.
Software latency may allow an overrun to occur between reads of
IRSCS1 and IRSCDR in the flag-clearing sequence.
shows the normal flag-clearing sequence and an example of an
overrun caused by a delayed flag-clearing sequence. The delayed
read of IRSCDR does not clear the OR bit because OR was not set
when IRSCS1 was read. Byte 2 caused the overrun and is lost. The
next flag-clearing sequence reads byte 3 in the IRSCDR instead of
byte 2.
In applications that are subject to software latency or in which it is
important to know which byte is lost due to an overrun, the flag-
clearing routine can check the OR bit in a second read of IRSCS1
after reading the data register.
This clearable, read-only bit is set when the SCI detects noise on the
RxD pin. NF generates an SCI error CPU interrupt request if the NEIE
bit in IRSCC3 is also set. Clear the NF bit by reading IRSCS1 and
then reading the IRSCDR. Reset clears the NF bit.
This clearable, read-only bit is set when a logic 0 is accepted as the
stop bit. FE generates an SCI error CPU interrupt request if the FEIE
bit in IRSCC3 also is set. Clear the FE bit by reading IRSCS1 with FE
set and then reading the IRSCDR. Reset clears the FE bit.
Freescale Semiconductor, Inc.
For More Information On This Product,
1 = Receive shift register full and SCRF = 1
0 = No receiver overrun
1 = Noise detected
0 = No noise detected
1 = Framing error detected
0 = No framing error detected
Go to: www.freescale.com
Infrared Serial Communications Interface Module (IRSCI)
Figure 14-16
I/O Registers
Data Sheet
281