MC68HC908AS60MFN MOTOROLA [Motorola, Inc], MC68HC908AS60MFN Datasheet - Page 359
MC68HC908AS60MFN
Manufacturer Part Number
MC68HC908AS60MFN
Description
HCMOS Microcontroller Unit
Manufacturer
MOTOROLA [Motorola, Inc]
Datasheet
1.MC68HC908AS60MFN.pdf
(454 pages)
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21.7.2 BDLC Control Register 1
MC68HC908AS60 — Rev. 1.0
MOTOROLA
Address:
BO3–BO0 — BARD Offset Bits
This register is used to configure and control the BDLC.
Reset:
Read:
Write:
Table 21-2
BARD offset values.
Freescale Semiconductor, Inc.
For More Information On This Product,
Byte Data Link Controller-Digital (BDLC-D)
$003C
IMSG
Bit 7
R
1
Figure 21-17. BDLC Control Register 1 (BCR1)
BARD Offset Bits BO[3:0]
Go to: www.freescale.com
shows the expected transceiver delay with respect to
= Reserved
CLKS
Table 21-2. BDLC Transceiver Delay
6
1
0000
0001
0010
0100
0101
1000
1001
1010
0011
0110
0111
1011
1100
1101
1110
1111
R1
5
1
R0
4
0
Byte Data Link Controller-Digital (BDLC-D)
Transceiver’s Delays ( s)
Corresponding Expected
R
3
0
0
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
9
R
2
0
0
BDLC CPU Interface
IE
1
0
Technical Data
WCM
Bit 0
0
359
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