MC68HC908LK24 MOTOROLA [Motorola, Inc], MC68HC908LK24 Datasheet - Page 113

• Manufacturer Part Number: MC68HC908LK24
• Description: Microcontrollers
• Manufacturer: MOTOROLA [Motorola, Inc]

MC68HC908LJ24/LK24 — Rev. 2
MOTOROLA
Addr.
$003A
$003B
$0036
$0037
$0038
$0039
NOTES:
1. When AUTO = 0, PLLIE is forced clear and is read-only.
2. When AUTO = 0, PLLF and LOCK read as clear.
3. When AUTO = 1, ACQ is read-only.
4. When PLLON = 0 or VRS7:VRS0 = $0, BCS is forced clear and is read-only.
5. When PLLON = 1, the PLL programming register is read-only.
6. When BCS = 1, PLLON is forced set and is read-only.
PLL VCO Range Select
PLL Bandwidth Control
PLL Reference Divider
Register Name
PLL Control Register
PLL Multiplier Select
PLL Multiplier Select
Select Register
Register High
Register Low
Register
Register
(PBWC)
(PMSH)
(PMRS)
(PMDS)
(PMSL)
(PTCL)
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Read:
Read:
Read:
Read:
Read:
Read:
Write:
Write:
Write:
Write:
Write:
Write:
Freescale Semiconductor, Inc.
Figure 8-2. CGM I/O Register Summary
For More Information On This Product,
PLLIE
AUTO
MUL7
VRS7
Bit 7
0
0
0
0
0
0
0
0
Clock Generator Module (CGM)
Go to: www.freescale.com
= Unimplemented
LOCK
MUL6
VRS6
PLLF
6
0
0
0
0
1
1
0
0
PLLON
MUL5
VRS5
ACQ
5
1
0
0
0
0
0
0
0
MUL4
VRS4
BCS
4
0
0
0
0
0
0
0
0
0
MUL11
PRE1
MUL3
VRS3
RDS3
R
3
0
0
0
0
0
0
0
Clock Generator Module (CGM)
= Reserved
MUL10
PRE0
MUL2
VRS2
RDS2
2
0
0
0
0
0
0
0
Functional Description
VPR1
MUL9
MUL1
VRS1
RDS1
1
0
0
0
0
0
0
0
Data Sheet
VPR0
MUL8
MUL0
VRS0
RDS0
Bit 0
R
0
0
0
0
0
1
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