DP84902M NSC [National Semiconductor], DP84902M Datasheet - Page 14

• Manufacturer Part Number: DP84902M
• Description: 1,7 Encoder/Decoder Circuit
• Manufacturer: NSC [National Semiconductor]

Functional Description
Precompensation Outputs
The precompensation circuit in this ENDEC generates out-
put data to be used externally to provide write precompen-
sation The precompensation truth table (Table V) demon-
strates what outputs are expected per data sequence (bit
stream) In the table the bit which is being considered for
CURRENT
STATE
0
0
0
0
1
1
1
1
2
2
2
2
3
3
3
3
4
4
4
4
NRZIO
TABLE IV Encoding State Table
M
B
S
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
B
L
S
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1 7 OUT
FIGURE 12 Hard Sectored Write Mode Waveforms
FIGURE 13 Hard Sectored Read Mode Waveforms
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
CODEOUT
(Continued)
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
1
1
1
0
STATE
NEXT
0
2
4
3
0
2
4
3
0
2
4
3
0
1
4
1
0
1
4
1
14
precompensation is the target bit T This target bit is a logi-
cal high level The location of data bits on either side of the
target bit indicates the logic states of the precompensation
outputs No shift indicates that all the precompensation out-
puts are at a logical low level The mention of a precompen-
sation output in the ‘‘FUNCTION’’ column indicates that it is
at a logical high while those not mentioned are at a logical
low level
The EARLY and LATE outputs need to be connected to
inputs of a precompensation circuit to achieve write pre-
compensation Using the NSC DP8492 device as an exam-
ple the EARLY and LATE outputs of the ENDEC will be
connected to the EARLY and LATE inputs to the DP8492
respectively
Address Mark Mode
Hard Sectored Read Mode (Figure 13)
This ENDEC supports only a 3T preamble pattern At the
assertion of READ GATE the decoder searches for 16 un-
interrupted code pulses of (3T) preamble Once the pream-
ble counter has filled to a count of 16 an internal preamble
detected signal is issued It resets an internal state machine
and initiates the phase synchronization process Decoding
of 1 7 data will begin after phase synchronization
Hard Sectored Write Mode (Figure 12)
At the assertion of WRITE GATE with NRZIO inputs held
low the encoder issues (3T) preamble at the CODEOUT
pin Preamble will continue until the first non-zero NRZ input
bit appears
0
1
1
0
TABLE V Precompensation Truth Table
MSB
0
0
0
0
BIT STREAM
T
T
T
T
0
0
0
0
LSB
0
1
0
1
FUNCTION
NO SHIFT
NO SHIFT
EARLY
LATE
TL F 11963 – 10
TL F 11963 – 9