AT89C51CC03CA-7CTUM ATMEL [ATMEL Corporation], AT89C51CC03CA-7CTUM Datasheet - Page 156
AT89C51CC03CA-7CTUM
Manufacturer Part Number
AT89C51CC03CA-7CTUM
Description
Enhanced 8-bit MCU with CAN Controller and Flash Memory
Manufacturer
ATMEL [ATMEL Corporation]
Datasheet
1.AT89C51CC03CA-7CTUM.pdf
(197 pages)
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Figure 75. A/D Converter Clock
ADC Standby Mode
IT ADC Management
Routines examples
156
AT89C51CC03
CPU Core Clock Symbol
CLOCK
CPU
When the ADC is not used, it is possible to set it in standby mode by clearing bit ADEN
in ADCON register. In this mode its power dissipation is about 1 µW.
An interrupt end-of-conversion will occurs when the bit ADEOC is activated and the bit
EADC is set. For re-arming the interrupt the bit ADEOC must be cleared by software.
Figure 76. ADC Interrupt Structure
1. Configure P1.2 and P1.3 in ADC channels
2. Start a standard conversion
3. Start a precision conversion (need interrupt ADC)
// configure channel P1.2 and P1.3 for ADC
// Enable the ADC
// The variable "channel" contains the channel to convert
// The variable "value_converted" is an unsigned int
// Clear the field SCH[2:0]
// Select channel
// Start conversion in standard mode
// Wait flag End of conversion
// Clear the End of conversion flag
// read the value
// The variable "channel" contains the channel to convert
// Enable ADC
ADCF = 0Ch
ADCON = 20h
ADCON and = F8h
ADCON | = channel
ADCON | = 08h
while((ADCON and 01h)! = 01h)
ADCON and = EFh
value_converted = (ADDH << 2)+(ADDL)
÷
2
ADEOC
ADCON.2
Prescaler ADCLK
EADC
IEN1.1
ADC Clock
ADCI
Converter
4182K–CAN–05/06
A/D
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