ISL8200AM INTERSIL [Intersil Corporation], ISL8200AM Datasheet
ISL8200AM
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ISL8200AM Summary of contents
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... Complete Current Share 10A DC/DC Power Module ISL8200AM The ISL8200AM is a simple and easy to use high power, current-sharing DC/DC power module for Datacom/Telecom/ FPGA power hungry applications. All that is needed is the ISL8200AM, a few passive components and one VOUT setting resistor to have a complete 10A design ready for market. ...
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... RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020 3. For Moisture Sensitivity Level (MSL), please see device information page for ISL8200AM. For more information on MSL please see techbrief TB363. Pinout Internal Circuit ...
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... The output current range is 15µA to 126µA typ. The ISET and ISHARE pins are used for current sharing purposes with multiple ISL8200AM modules. In the single module configuration, this pin can be tied to the ISHARE pin. In multi-phase operation, if noise is a concern, add an additional 10pF capacitor to the ISET line ...
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... FSYNC_IN and PGND1 is recommended. 8 CLKOUT Digital Voltage Output - This pin provides a clock signal to synchronize with other ISL8200AM(s). When there is more than one ISL8200AM in the system, the two independent regulators can be programmed via PH_CNTRL for different degrees of phase delay. ...
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... ISFETDRV1 SET R1 AND R2 SUCH THAT 0.8V ≤ VEN ≤ 5.0V DO NOT TIE EN DIRECTLY TO A POWER SOURCE 5 ISL8200AM PIN DESCRIPTION PVIN VOUT VIN VOUT_SET FF VSEN_REM- EN ISL8200AM FSYNC_IN PGOOD CLKOUT PH_CNTRL ISHARE_BUS ISFETDRV FIGURE 3. SINGLE PHASE 10A 1.2V OUTPUT CIRCUIT VOUT RSET 2.2k PGOOD VCC VCC RSET CAN CHANGE VOUT ...
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... VOUT_SET FF VSEN_REM- EN ISL8200AM FSYNC_IN PGOOD CLKOUT PH_CNTRL ISHARE_BUS VCC ISFETDRV ISHARE PVIN VOUT VIN VOUT_SET FF VSEN_REM- EN ISL8200AM FSYNC_IN PGOOD CLKOUT PH_CNTRL ISHARE_BUS VCC ISFETDRV ISHARE FIGURE 4. TWO PHASE 20A 3.3V OUTPUT CIRCUIT VOUT VOUT C9 100µF (x6) RSET1 10k GROUND 2.2nF PGOOD VCC1 ...
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... Turn-On Threshold Voltage Hysteresis Sink Current Undervoltage Lockout Hysteresis Sink Current Sink Impedance OSCILLATOR Oscillator Frequency Total Variation (Note 7) 7 ISL8200AM Thermal Information Thermal Resistance (Typical) QFN Package (Notes Maximum Storage Temperature Range . . . . . . . . . . . . . .-55°C to +150° 0.3V BOOT BOOT Recommended Operating Conditions + 0 ...
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... OVERCURRENT PROTECTION (Note 7) Channel Overcurrent Limit Channel Overcurrent Limit Share Pin OC Threshold CURRENT SHARE External Current Share Accuracy POWER GOOD MONITOR (Note 7) Undervoltage Falling Trip Point Undervoltage Rising Hysteresis Overvoltage Rising Trip Point 8 ISL8200AM SYMBOL TEST CONDITIONS 5.4V 700kHz CC SW ...
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... Parameters with TYP limits are not production tested, unless otherwise specified. 7. Parameters with MIN and/or MAX limits are 100% tested for internal IC prior to module assembly, unless otherwise specified. Temperature limits established by characterization and are not production tested. 9 ISL8200AM SYMBOL TEST CONDITIONS V ...
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... FIGURE 6. EFFICIENCY vs LOAD CURRENT (5V 100 3.3V 2. LOAD CURRENT (A) FIGURE 8. EFFICIENCY vs LOAD CURRENT (20V 10 ISL8200AM PVIN VIN VOUT_SET FF VSEN_REM- EN ISL8200AM FSYNC_IN PGOOD CLKOUT PH_CNTRL ISHARE_BUS ISFETDRV = +25° 220µFx1, 10µF/Ceramic 100 1.5V 70 1.2V 0. ...
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... 1.5V OUT OUT FIGURE 10. 1.5V TRANSIENT RESPONSE V OUT V = 12V 2.5V OUT OUT FIGURE 12. 2.5V TRANSIENT RESPONSE 11 ISL8200AM (Continued +25° 12V 5A, Current slew rate = 2.5A/µs OUT V = 12V IN V OUT OUT PHASE1-M ...
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... NO LOAD OUT V 5A OUT V 10A OUT FIGURE 17. 1.2V OUTPUT RIPPLE V NO LOAD OUT V 5A OUT V 10A OUT FIGURE 19. 2.5V OUTPUT RIPPLE 12 ISL8200AM (Continued +25° 12V 220µFx1, 10µF/Ceramic 100µF/Ceramic Load OUT OUT ...
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... Applications Information Programming the Output Voltage (R The ISL8200AM has an internal 0.6V ± 0.7% reference voltage. Programming the output voltage requires a dividing resistor (R ) between the VOUT_SET pin and the V SET The output voltage can be calculated as shown in Equation 1: R ⎛ ⎞ SET × V 0.6 ⎜ 1 ⎟ ...
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... ISHARE Functional Description Initialization The ISL8200AM requires VCC and PVCC to be biased by a single supply. Power-On Reset (POR) circuits continually monitor the bias voltages (PVCC and VCC) and the voltage at the EN pin. The POR function initiates soft-start operation 384 clock cycles after the EN pin voltage is pulled to be above 0.8V ...
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... The ISL8200AM has the ability to work under a pre-charged output. The PWM outputs will not be fed to the drivers until the first PWM pulse is seen. The low side MOSFET is held low for the first clock cycle to provide charge for the bootstrap capacitor. If the ...
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... R current I OUT(MAX) during turn on through the resistor between . V is compared with a ISHARE ISHARE to be scaled ISHARE of 2.2kΩ, the OCP level is set to the ISEN-IN ISEN-EX values and the typical output ISEN-EX OCP levels for ISL8200AM are shown in September 13, 2012 ) ISHARE is FN8271.2 ...
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... PGND1 from the FSYNC_IN pin, the switching frequency can be set at any frequency between 700kHz and 1.5MHz. The ISL8200AM has an integrated 59kΩ resistor between FSYNC_IN and PGND1, which sets the default frequency to 700kHz. The frequency setting curve shown in Figure 34 is ...
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... FIGURE 34. RFS-ext vs SWITCHING FREQUENCY By connecting the FSYNC_IN pin to an external square pulse waveform (such as the CLKOUT signal, typically 50% duty cycle from another ISL8200AM), the ISL8200AM will synchronize its switching frequency to the fundamental frequency of the input waveform. The voltage range on the FSYNC_IN pin ...
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... ISL8200AM CLKOUT to FSYNC_IN TO LOAD GND TO VOUT RFBT CEN CPVCC CIN COUT FIGURE 36. RECOMMENDED LAYOUT FOR DUAL PHASE SETUP 19 EN ISHARE CEN CPVCC CIN COUT TO LOAD GND TO VOUT RFBT FN8271.2 September 13, 2012 ...
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... These guidelines are general design rules. Users could modify parameters according to their application. PCB Layout Pattern Design The bottom of ISL8200AM is a lead-frame footprint, which is attached to the PCB by surface mounting process. The PCB layout pattern is shown in the Package Outline Drawing L23.15x15 on page 23. The PCB layout pattern is essentially 1:1 ...
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... A 0.1mm to 0.15mm stencil thickness is recommended for this large pitch (1.3mm) QFN. 21 ISL8200AM Reflow Parameters Due to the low mount height of the QFN, "No Clean" Type 3 solder paste per ANSI/J-STD-005 is recommended. Nitrogen purge is also recommended during reflow. A system board reflow profile ...
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... However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see 22 ISL8200AM Initial Release. www.intersil.com/askourstaff For additional products, see www ...
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Package Outline Drawing L23.15x15 23 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE (PUNCH QFN) Rev 3, 10/ 15.0±0.2 ...
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TYPICAL RECOMMENDED LAND PATTERN 6.23 4.18 3.88 1.83 1.53 0.00 0.52 0.82 2.87 ...