U6264ADC07 ETC [List of Unclassifed Manufacturers], U6264ADC07 Datasheet

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U6264ADC07

Manufacturer Part Number
U6264ADC07
Description
STANDARD 8K X 8 SRAM
Manufacturer
ETC [List of Unclassifed Manufacturers]
Datasheet
December 12, 1997
Features
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Pin Configuration
8192 x 8 bit static CMOS RAM
70 and 100 ns Access Times
Common data inputs and
outputs
Three-state outputs
Typ. operating supply current
Data retention current
at 3 V: < 10
Standby current standard < 30 A
Standby current low power
(L) < 10 A
Standby current very low power
(LL) < 1 A
Standby current for LL-version
at 25 C and 5 V: typ. 50 nA
TTL/CMOS-compatible
Automatic reduction of power
dissipation in long Read or Write
cycles
Power supply voltage 5 V
Operating temperature ranges:
Quality assessment according to
CECC 90000, CECC 90100 and
CECC 90111
DQ1
DQ2
DQ0
VSS
A12
n.c.
A7
A6
A5
A4
A3
A2
A1
A0
100 ns: 37 mA
-25 to 85 C
-40 to 85 C
70 ns: 45 mA
0 to 70 C
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Top View
PDIP
A (standard)
SOP
28
27
26
25
24
23
22
21
20
19
18
17
16
15
DQ3
VCC
W (WE)
E2 (CE2)
A8
A9
A11
G (OE)
A10
E1 (CE1)
DQ7
DQ6
DQ5
DQ4
F
F
F
Description
The U6264A is a static RAM manu-
factured using a CMOS process
technology with the following ope-
rating modes:
- Read
- Write
The memory array is based on a
6-transistor cell.
The circuit is activated by the rising
edge of E2 (at E1 = L), or the falling
edge of E1 (at E2 = H). The
address and control inputs open
simultaneously. According to the
information of W and G, the data
inputs, or outputs, are active.
During the active state (E1 = L and
E2 = H), each address change
leads to a new Read or Write cycle.
In a Read cycle, the data outputs
are activated by the falling edge of
G, afterwards the data word read
will be available at the outputs
ESD protection > 2000 V
(MIL STD 883C M3015.7)
Latch-up immunity > 100 mA
Packages: PDIP28 (600 mil)
- Standby
- Data Retention
1
SOP28 (300 mil)
SOP28 (330 mil)
Pin Description
Signal Name
A0 - A12
DQ0 - DQ7
E1
E2
G
W
VCC
VSS
n.c.
Signal Description
Address Inputs
Data In/Out
Chip Enable 1
Chip Enable 2
Output Enable
Write Enable
Power Supply Voltage
Ground
not connected
DQ0 - DQ7. After the address
change, the data outputs go High-Z
until the new read information is
available. The data outputs have no
preferred state. If the memory is
driven by CMOS levels in the active
state, and if there is no change of
the address, data input and control
signals W or G, the operating cur-
rent (at I
value of the operating current in the
Standby mode. The Read cycle is
finished by the falling edge of E2 or
W, or by the rising edge of E1,
respectively.
Data retention is guaranteed down
to 2 V. With the exception of E2, all
inputs consist of NOR gates, so that
no pull-up/pull-down resistors are
required. This gate circuit allows to
achieve low power standby require-
ments by activation with TTL-levels
too.
If the circuit is inactivated by
E2 = L, the standby current (TTL)
drops to 150 A typ.
Standard 8K x 8 SRAM
O
= 0 mA) drops to the
U6264A

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U6264ADC07 Summary of contents

Page 1

Features F 8192 x 8 bit static CMOS RAM F 70 and 100 ns Access Times F Common data inputs and outputs F Three-state outputs F Typ. operating supply current 70 ns 100 ns Data ...

Page 2

U6264A Block Diagram A11 A12 A10 E2 E1 Truth Table Operating Mode E1 * Standby/not selected H Internal Read L Read L Write Characteristics All ...

Page 3

Recommended Operating Conditions Power Supply Voltage Data Retention Voltage Input Low Voltage* Input High Voltage * - Pulse Width 10 ns Electrical Characteristics Supply Current - Operating Mode Standard Low Power (L) Very Low Power (LL) Supply Current ...

Page 4

U6264A Electrical Characteristics Output High Voltage Output Low Voltage Input Leakage Current Standard & Low Power (L) High Low Very Low Power (LL) High Low Output High Current Output Low Current Output Leakage Current Standard & Low Power (L) High ...

Page 5

Switching Characteristics Time to Output in Low-Z Cycle Time Write Cycle Time Read Cycle Time Access Time E1 LOW or E2 HIGH to Data Valid G LOW to Data Valid Address to Data Valid Pulse Widths Write Pulse Width Chip ...

Page 6

U6264A Test Configuration for Functional Check measurement dis(E) dis(W) Capacitance Input Capacitance Output Capacitance All pins not under test must be connected with ground by capacitors. IC Code Numbers Example ...

Page 7

Read Cycle 1 (during Read cycle Previous Data Valid Output Read Cycle 2 (during Read cycle Output Write Cycle 1 (W-controlled) ...

Page 8

U6264A Write Cycle 2 (E1-controlled AAAA AAAA AAAA AAAA AAAA AAAA E2 AAAA AAAA AAAA AAAA AAAA AAAA W AAAA AAAA AAAA AAAA DQ i Input DQ i Output G Write Cycle 3 (E2-controlled AAAA ...

Page 9

Memory Products 1998 Standard SRAM U6264A LIFE SUPPORT POLICY ZMD products are not designed, intended, or authorized for use as components in systems intend for surgical implant into the body, or other applications intended to support or ...

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