HD6412320 RENESAS [Renesas Technology Corp], HD6412320 Datasheet - Page 1153
HD6412320
Manufacturer Part Number
HD6412320
Description
Renesas 16-Bit Single-Chip Microcomputer H8S Family H8S-2300 Series
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet
1.HD6412320.pdf
(1302 pages)
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Short address mode
Bit
DMACR
Initial value
Read/Write
Data Transfer Size
0
1
Data Transfer Increment/Decrement
Byte-size transfer
Word-size transfer
0
1
:
:
:
:
MAR is incremented after a data transfer
MAR is decremented after a data transfer
DTSZ
R/W
Repeat Enable
7
0
0
1
Transfer in sequential mode
Transfer in repeat mode or idle mode
DTID
R/W
Data Transfer Direction
6
0
0
1
Dual address mode: Transfer with
MAR as source address and IOAR
as destination address
Single address mode: Transfer with
MAR as source address and DACK
pin as write strobe
Dual address mode: Transfer with
IOAR as source address and MAR
as destination address
Single address mode: Transfer with
DACK pin as read strobe and MAR
as destination address
RPE
R/W
5
0
DTDIR
R/W
4
0
DTF3
R/W
3
0
DTF2
R/W
2
0
Rev.6.00 Sep. 27, 2007 Page 1123 of 1268
Data Transfer Factor
DTF
3
0
1
DTF1
R/W
DTF
1
0
2
0
1
0
1
DTF
0
1
0
1
0
1
0
1
1
Appendix B Internal I/O Registers
DTF0
DTF
R/W
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
0
—
Activated by A/D converter conversion
end interrupt
—
—
Activated by SCI channel 0 transmission
data-empty interrupt
Activated by SCI channel 0 reception
data-full interrupt
Activated by SCI channel 1 transmission
data-empty interrupt
Activated by SCI channel 1 reception
data-full interrupt
Activated by TPU channel 0 compare
match/input capture A interrupt
Activated by TPU channel 1 compare
match/input capture A interrupt
Activated by TPU channel 2 compare
match/input capture A interrupt
Activated by TPU channel 3 compare
match/input capture A interrupt
Activated by TPU channel 4 compare
match/input capture A interrupt
Activated by TPU channel 5 compare
match/input capture A interrupt
—
—
Channel A
REJ09B0220-0600
Activated by DREQ pin
falling edge input
Activated by DREQ pin
low-level input
Channel B
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