HD6412340 HITACHI [Hitachi Semiconductor], HD6412340 Datasheet - Page 115
HD6412340
Manufacturer Part Number
HD6412340
Description
H8S/2345 F-ZTAT Hardware Manual
Manufacturer
HITACHI [Hitachi Semiconductor]
Datasheet
1.HD6412340.pdf
(907 pages)
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4.2.3
The H8S/2345 Series enters the reset state when the RES pin goes low.
To ensure that the H8S/2345 Series is reset, hold the RES pin low for at least 20 ms at power-up.
To reset the H8S/2345 Series during operation, hold the RES pin low for at least 20 states.
When the RES pin goes high after being held low for the necessary time, the H8S/2345 Series
starts reset exception handling as follows:
1. The internal state of the CPU and the registers of the on-chip supporting modules are
2. The reset exception handling vector address is read and transferred to the PC, and program
Figures 4.2 and 4.3 show examples of the reset sequence.
initialized, the T bit is cleared to 0 in EXR, and the I bit is set to 1 in EXR and CCR.
execution starts from the address indicated by the PC.
RES
Internal
address bus
Internal read
signal
Internal write
signal
Internal data
bus
Reset Sequence
ø
(1) Reset exception handling vector address ((1) = H'0000)
(2) Start address (contents of reset exception handling vector address)
(3) Start address ((3) = (2))
(4) First program instruction
Figure 4.2 Reset Sequence (Modes 2 and 3)
Vector
fetch
(1)
(2)
Internal
processing
High
Prefetch of first program
instruction
(3)
(4)
95
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