HD6412340 HITACHI [Hitachi Semiconductor], HD6412340 Datasheet - Page 197
HD6412340
Manufacturer Part Number
HD6412340
Description
H8S/2345 F-ZTAT Hardware Manual
Manufacturer
HITACHI [Hitachi Semiconductor]
Datasheet
1.HD6412340.pdf
(907 pages)
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7.2.3
SAR is a 24-bit register that designates the source address of data to be transferred by the DTC.
For word-size transfer, specify an even source address.
7.2.4
Bit
Initial value
R/W
DAR is a 24-bit register that designates the destination address of data to be transferred by the
DTC. For word-size transfer, specify an even destination address.
7.2.5
CRA is a 16-bit register that designates the number of times data is to be transferred by the DTC.
In normal mode, the entire CRA functions as a 16-bit transfer counter (1 to 65536). It is
decremented by 1 every time data is transferred, and transfer ends when the count reaches H'0000.
In repeat mode or block transfer mode, the CRA is divided into two parts: the upper 8 bits
(CRAH) and the lower 8 bits (CRAL). CRAH holds the number of transfers while CRAL
functions as an 8-bit transfer counter (1 to 256). CRAL is decremented by 1 every time data is
transferred, and the contents of CRAH are sent when the count reaches H'00. This operation is
repeated.
Bit
Initial value
R/W
Bit
Initial value
R/W
DTC Source Address Register (SAR)
DTC Destination Address Register (DAR)
DTC Transfer Count Register A (CRA)
:
:
:
:
:
:
:
:
:
Unde-
Unde-
fined
fined
Unde-
23
15
—
—
fined
23
—
Unde-
Unde-
fined
fined
Unde-
22
14
—
fined
—
22
—
Unde-
Unde-
fined
fined
Unde-
21
13
—
fined
—
21
—
Unde-
Unde-
fined
fined
Unde-
20
12
fined
—
—
20
CRAH
—
Unde-
Unde-
fined
fined
Unde-
19
11
fined
—
—
19
—
Unde-
fined
10
—
Unde-
fined
—
9
Unde-
fined
—
8
Unde-
fined
—
7
Unde-
fined
—
6
Unde-
fined
—
5
Unde-
Unde-
Unde-
fined
fined
fined
—
—
—
4
4
4
CRAL
Unde-
Unde-
Unde-
fined
fined
fined
—
—
—
3
3
3
Unde-
Unde-
Unde-
fined
fined
fined
—
—
—
2
2
2
Unde-
Unde-
Unde-
fined
fined
fined
—
—
—
1
1
1
Unde-
Unde-
Unde-
fined
fined
fined
179
—
—
—
0
0
0
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