HD6412340 HITACHI [Hitachi Semiconductor], HD6412340 Datasheet - Page 209
HD6412340
Manufacturer Part Number
HD6412340
Description
H8S/2345 F-ZTAT Hardware Manual
Manufacturer
HITACHI [Hitachi Semiconductor]
Datasheet
1.HD6412340.pdf
(907 pages)
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7.3.6
In repeat mode, one operation transfers one byte or one word of data.
From 1 to 256 transfers can be specified. Once the specified number of transfers have ended, the
initial state of the transfer counter and the address register specified as the repeat area is restored,
and transfer is repeated. In repeat mode the transfer counter value does not reach H'00, and
therefore CPU interrupts cannot be requested when DISEL = 0.
Table 7.6 lists the register information in repeat mode and figure 7.7 shows memory mapping in
repeat mode.
Table 7.6
Name
DTC source address register
DTC destination address register
DTC transfer count register AH
DTC transfer count register AL
DTC transfer count register B
SAR or
DAR
Repeat Mode
Register Information in Repeat Mode
Repeat area
Figure 7.7 Memory Mapping in Repeat Mode
Abbreviation
SAR
DAR
CRAH
CRAL
CRB
Transfer
Function
Designates source address
Designates destination address
Holds number of transfers
Designates transfer count (8 bits
Not used
DAR or
SAR
191
2)
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