HD6412340 HITACHI [Hitachi Semiconductor], HD6412340 Datasheet - Page 232
HD6412340
Manufacturer Part Number
HD6412340
Description
H8S/2345 F-ZTAT Hardware Manual
Manufacturer
HITACHI [Hitachi Semiconductor]
Datasheet
1.HD6412340.pdf
(907 pages)
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Table 8.3
Pin
P1
TCLKB/A
3
/TIOCD0/
23
Port 1 Pin Functions (cont)
Selection Method and Pin Functions
The pin function is switched as shown below according to the combination of
the operating mode, TPU channel 0 setting (by bits MD3 to MD0 in TMDR0,
bits IOD3 to IOD0 in TIOR0L, and bits CCLR2 to CCLR0 in TCR0), bits TPSC2
to TPSC0 in TCR0 to TCR2, and bit P13DDR.
Notes: 1. Modes 1 to 3 are not available on the F-ZTAT version.
Operating
Mode
TPU Channel
0 Setting
P13DDR
Pin function
TPU Channel
0 Setting
MD3 to MD0
IOD3 to IOD0
CCLR2 to
CCLR0
Output
function
2. TIOCD0 input when TPU channel 0 is in normal operation mode
3. TCLKB input when the TCR0, TCR1, or TCR2 setting is: TPSC2 to
Modes 2, 3, 6, and 7 are not available on the ROMless version.
(MD3 to MD0 = B'0000) and input capture is set (IOD3 to IOD0 =
B'10xx).
TPSC0 = B'101.
TCLKB input when channels 1 and 5 are set to phase counting
mode (MD3 to MD0 = B'01xx).
B'0000
B'0100
B'1xxx
Below (1)
TIOCD0
(2)
output
—
—
Table
Modes 1, 2, 3, 7*
—
B'0000
B'0001 to
B'0011
B'0101 to
B'0111
compare
Output
output
(1)
—
input
P1
Below (2)
0
TIOCD0
input*
Table
3
B'0010
output
1
TCLKB input*
P1
(2)
2
—
—
—
1
3
TIOCD0
output
B'xx00
Below (1)
0
Table
(2)
—
—
3
Modes 4, 5, 6*
output
A
1
23
Other than B'xx00
B'0011
mode 2
output
Other
B'110
PWM
than
(1)
input
P1
Below (2)
0
x: Don’t care
TIOCD0
input*
Table
3
1
B'110
output
(2)
—
A
2
1
23
215
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