HD6412340 HITACHI [Hitachi Semiconductor], HD6412340 Datasheet - Page 249
HD6412340
Manufacturer Part Number
HD6412340
Description
H8S/2345 F-ZTAT Hardware Manual
Manufacturer
HITACHI [Hitachi Semiconductor]
Datasheet
1.HD6412340.pdf
(907 pages)
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Port 3 Register (PORT3)
PORT3 is an 8-bit read-only register that shows the pin states. Writing of output data for the port 3
pins (P3
Bits 7 and 6 are reserved; they return an undetermined value if read, and cannot be modified.
If a port 3 read is performed while P3DDR bits are set to 1, the P3DR values are read. If a port 3
read is performed while P3DDR bits are cleared to 0, the pin states are read.
After a power-on reset and in hardware standby mode, PORT3 contents are determined by the pin
states, as P3DDR and P3DR are initialized. PORT3 retains its prior state after a manual reset, and
in software standby mode.
Port 3 Open Drain Control Register (P3ODR)
P3ODR is an 8-bit readable/writable register that controls the PMOS on/off status for each port 3
pin (P3
Bits 7 and 6 are reserved; they return an undetermined value if read, and cannot be modified.
Setting a P3ODR bit to 1 makes the corresponding port 3 pin an NMOS open-drain output pin,
while clearing the bit to 0 makes the pin a CMOS output pin.
P3ODR is initialized to H'00 (bits 5 to 0) by a power-on reset, and in hardware standby mode. It
retains its prior state after a manual reset, and in software standby mode.
232
Bit
Initial value
R/W
Note: * Determined by state of pins P3
Bit
Initial value
R/W
5
5
to P3
to P3
:
:
:
0
:
:
:
).
0
) must always be performed on P3DR.
Undefined
Undefined
—
—
—
—
7
7
Undefined
Undefined
—
—
—
—
6
6
P35ODR
5
R/W
P35
—*
to P3
R
5
5
0
0
.
P34ODR
R/W
P34
—*
R
4
4
0
P33ODR
R/W
P33
—*
R
3
3
0
P32ODR
R/W
P32
—*
R
2
2
0
P31ODR
R/W
P31
—*
R
1
1
0
P30ODR
R/W
P30
—*
R
0
0
0
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