HD6412340 HITACHI [Hitachi Semiconductor], HD6412340 Datasheet - Page 294
HD6412340
Manufacturer Part Number
HD6412340
Description
H8S/2345 F-ZTAT Hardware Manual
Manufacturer
HITACHI [Hitachi Semiconductor]
Datasheet
1.HD6412340.pdf
(907 pages)
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9.1
The H8S/2345 Series has an on-chip 16-bit timer pulse unit (TPU) that comprises six 16-bit timer
channels.
9.1.1
Maximum 16-pulse input/output
Selection of 8 counter input clocks for each channel
The following operations can be set for each channel:
Buffer operation settable for channels 0 and 3
Phase counting mode settable independently for each of channels 1, 2, 4, and 5
Cascaded operation
Fast access via internal 16-bit bus
A total of 16 timer general registers (TGRs) are provided (four each for channels 0 and 3,
TGRC and TGRD for channels 0 and 3 can also be used as buffer registers
Waveform output at compare match: Selection of 0, 1, or toggle output
Input capture function: Selection of rising edge, falling edge, or both edge detection
Counter clear operation: Counter clearing possible by compare match or input capture
Synchronous operation: Multiple timer counters (TCNT) can be written to simultaneously
PWM mode: Any PWM output duty can be set
Input capture register double-buffering possible
Automatic rewriting of output compare register possible
Two-phase encoder pulse up/down-count possible
Channel 2 (channel 5) input clock operates as 32-bit counter by setting channel 1 (channel
Fast access is possible via a 16-bit bus interface
and two each for channels 1, 2, 4, and 5), each of which can be set independently as an
output compare/input capture register
Simultaneous clearing by compare match and input capture possible
Register simultaneous input/output possible by counter synchronous operation
Maximum of 15-phase PWM output possible by combination with synchronous operation
4) overflow/underflow
Overview
Features
Section 9 16-Bit Timer Pulse Unit (TPU)
277
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