HD6412340 HITACHI [Hitachi Semiconductor], HD6412340 Datasheet - Page 387
HD6412340
Manufacturer Part Number
HD6412340
Description
H8S/2345 F-ZTAT Hardware Manual
Manufacturer
HITACHI [Hitachi Semiconductor]
Datasheet
1.HD6412340.pdf
(907 pages)
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10.1
The H8S/2345 Series includes an 8-bit timer module with two channels (TMR0 and TMR1). Each
channel has an 8-bit counter (TCNT) and two time constant registers (TCORA and TCORB) that
are constantly compared with the TCNT value to detect compare match events. The 8-bit timer
module can thus be used for a variety of functions, including pulse output with an arbitrary duty
cycle.
10.1.1
The features of the 8-bit timer module are listed below.
Selection of four clock sources
The counters can be driven by one of three internal clock signals (ø/8, ø/64, or ø/8192) or an
external clock input (enabling use as an external event counter).
Selection of three ways to clear the counters
The counters can be cleared on compare match A or B, or by an external reset signal.
Timer output control by a combination of two compare match signals
The timer output signal in each channel is controlled by a combination of two independent
compare match signals, enabling the timer to generate output waveforms with an arbitrary duty
cycle or PWM output.
Provision for cascading of two channels
Three independent interrupts
Compare match A and B and overflow interrupts can be requested independently.
A/D converter conversion start trigger can be generated
Channel 0 compare match A signal can be used as an A/D converter conversion start trigger.
Module stop mode can be set
Operation as a 16-bit timer is possible, using channel 0 for the upper 8 bits and channel 1
Channel 1 can be used to count channel 0 compare matches (compare match count mode).
for the lower 8 bits (16-bit count mode).
As the initial setting, 8-bit timer operation is halted. Register access is enabled by exiting
module stop mode.
Overview
Features
Section 10 8-Bit Timers
371
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