HD6412340 HITACHI [Hitachi Semiconductor], HD6412340 Datasheet - Page 458
HD6412340
Manufacturer Part Number
HD6412340
Description
H8S/2345 F-ZTAT Hardware Manual
Manufacturer
HITACHI [Hitachi Semiconductor]
Datasheet
1.HD6412340.pdf
(907 pages)
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Figure 12.4 shows a sample SCI initialization flowchart.
SCR to 1, and set RIE, TIE, TEIE,
Clear TE and RE bits in SCR to 0
Set CKE1 and CKE0 bits in SCR
Set data transfer format in
<Transfer completion>
1-bit interval elapsed?
Set TE and RE bits in
Set value in BRR
Start initialization
SMR and SCMR
(TE, RE bits 0)
and MPIE bits
Figure 12.4 Sample SCI Initialization Flowchart
Yes
Wait
No
[1]
[2]
[3]
[4]
[1] Set the clock selection in SCR.
[2] Set the data transfer format in SMR
[3] Write a value corresponding to the
[4] Wait at least one bit interval, then
Be sure to clear bits RIE, TIE,
TEIE, and MPIE, and bits TE and
RE, to 0.
When the clock is selected in
asynchronous mode, it is output
immediately after SCR settings are
made.
and SCMR.
bit rate to BRR. Not necessary if an
external clock is used.
set the TE bit or RE bit in SCR to 1.
Also set the RIE, TIE, TEIE, and
MPIE bits.
Setting the TE and RE bits enables
the TxD and RxD pins to be used.
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