HD6412340 HITACHI [Hitachi Semiconductor], HD6412340 Datasheet - Page 530
HD6412340
Manufacturer Part Number
HD6412340
Description
H8S/2345 F-ZTAT Hardware Manual
Manufacturer
HITACHI [Hitachi Semiconductor]
Datasheet
1.HD6412340.pdf
(907 pages)
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14.4.3
The A/D converter has a built-in sample-and-hold circuit. The A/D converter samples the analog
input at a time t
conversion timing. Table 14.4 indicates the A/D conversion time.
As indicated in figure 14.5, the A/D conversion time includes t
length of t
time therefore varies within the ranges indicated in table 14.4.
In scan mode, the values given in table 14.4 apply to the first conversion time. In the second and
subsequent conversions the conversion time is fixed at 256 states when CKS = 0 or 128 states
when CKS = 1.
Input Sampling and A/D Conversion Time
D
ø
Input sampling
timing
ADF
Address bus
Write signal
varies depending on the timing of the write access to ADCSR. The total conversion
Legend
(1)
(2)
t
t
t
D
SPL
CONV
D
after the ADST bit is set to 1, then starts conversion. Figure 14.5 shows the A/D
: ADCSR write cycle
: ADCSR address
: A/D conversion start delay
: Input sampling time
: A/D conversion time
(1)
(2)
Figure 14.5 A/D Conversion Timing
t
D
t
SPL
t
CONV
D
and the input sampling time. The
517
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