HD6412340 HITACHI [Hitachi Semiconductor], HD6412340 Datasheet - Page 619
HD6412340
Manufacturer Part Number
HD6412340
Description
H8S/2345 F-ZTAT Hardware Manual
Manufacturer
HITACHI [Hitachi Semiconductor]
Datasheet
1.HD6412340.pdf
(907 pages)
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V
FWE
MD
RES
SWE bit
Notes: 1. In transition to the boot mode and transition from the boot mode to another mode, mode switching via RES
CC
2
to MD
Flash memory access disabled period
(x: Wait time after SWE setting)
Flash memory reprogammable period
(Flash memory program execution and data read, other than verify, are disabled.)
2. When making a transition from the boot mode to another mode, the mode programming setup time t
3. See section 20.1.6 Flash Memory Characteristics.
0
input is necessary.
During this switching period (period during which a low level is input to the RES pin), the state of the address
dual port and bus control output signals (AS, RD, HUR, LWR) changes.
Therefore, do not use these pins as output signals during this switching period.
relative to the RES clear timing is necessary.
Mode switching *
t
(Example: Boot Mode
OSC1
SWE set
t
Wait time: x
MDS
t
MDS
1
Figure 17.38 Mode Transition Timing
Boot mode
*3
Programming and
erase possible
SWE clear
Mode
switching *
t
RESW
Min 0 s
t
MDS
User Mode
*2
Wait time: x
1
User
mode
Programming
possible
erase
User program mode
and
User Program Mode
Wait
time: x
Programming and
erase possible
User
mode
Wait
time: x
User
program
mode
Programming
MDS
possible
erase
and
607
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