HD6412340 HITACHI [Hitachi Semiconductor], HD6412340 Datasheet - Page 755
HD6412340
Manufacturer Part Number
HD6412340
Description
H8S/2345 F-ZTAT Hardware Manual
Manufacturer
HITACHI [Hitachi Semiconductor]
Datasheet
1.HD6412340.pdf
(907 pages)
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Table A.6 Instruction Execution Cycles (cont)
Notes: 1. EAs is the contents of ER5. EAd is the contents of ER6.
XOR.L ERs,ERd
XORC #xx:8,CCR
XORC #xx:8,EXR
Reset exception
handling
Interrupt exception
handling
Instruction
2. EAs is the contents of ER5. EAd is the contents of ER6. Both registers are incremented by 1 after execution of the instruction. n is the initial
3. Repeated two times to save or restore two registers, three times for three registers, or four times for four registers.
4. Start address after return.
5. Start address of the program.
6. Prefetch address, equal to two plus the PC value pushed onto the stack. In recovery from sleep mode or software standby mode the read
7. Start address of the interrupt-handling routine.
value of R4L or R4. If n = 0, these bus cycles are not executed.
operation is replaced by an internal operation.
R:W 2nd
R:W NEXT
R:W 2nd
R:W:M VEC
R:W
*
1
6
R:W NEXT
R:W NEXT
R:W VEC+2
Internal operation, W:W stack (L)
1 state
2
Internal operation, R:W
1 state
3
W:W stack (H)
*
4
5
W:W stack (EXR)
5
R:W:M VEC
6
R:W VEC+2
7
Internal operation, R:W
1 state
8
*
9
7
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