HD6412340 HITACHI [Hitachi Semiconductor], HD6412340 Datasheet - Page 785
HD6412340
Manufacturer Part Number
HD6412340
Description
H8S/2345 F-ZTAT Hardware Manual
Manufacturer
HITACHI [Hitachi Semiconductor]
Datasheet
1.HD6412340.pdf
(907 pages)
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TCR5—Timer Control Register 5
776
Bit
Initial value
Read/Write
:
:
:
—
—
7
0
Note: * Synchronous operating setting is performed by setting
Counter Clear
0
1
CCLR1
R/W
0
1
0
1
6
0
the SYNC bit TSYR to 1.
TCNT clearing disabled
TCNT cleared by TGRA compare match/input capture
TCNT cleared by TGRB compare match/input capture
TCNT cleared by counter clearing for another channel
performing synchronous clearing/synchronous operation*
CCLR0
R/W
5
0
Note: This setting is ignored when channel
Clock Edge
CKEG1
0
1
R/W
4
0
5 is in phase counting mode.
—
0
1
Count at rising edge
Count at falling edge
Count at both edges
CKEG0
R/W
3
0
Note:
Time Prescaler
H'FEA0
0
1
TPSC2
R/W
This setting is ignored when channel 5 is in phase
counting mode.
0
1
0
1
2
0
0
1
0
1
0
1
0
1
Internal clock: counts on ø/1
Internal clock: counts on ø/4
Internal clock: counts on ø/16
Internal clock: counts on ø/64
External clock: counts on TCLKA pin input
External clock: counts on TCLKC pin input
Internal clock: counts on ø/256
External clock: counts on TCLKD pin input
TPSC1
R/W
1
0
TPSC0
R/W
0
0
TPU5
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