HD6412373R RENESAS [Renesas Technology Corp], HD6412373R Datasheet - Page 128
HD6412373R
Manufacturer Part Number
HD6412373R
Description
Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2300 Series
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet
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Section 2 CPU
Table 2.9
Instruction
TRAPA
RTE
SLEEP
LDC
STC
ANDC
ORC
XORC
NOP
Note:
Rev.7.00 Mar. 18, 2009 page 60 of 1136
REJ09B0109-0700
* Size refers to the operand size.
B: Byte
W: Word
System Control Instructions
Size *
—
—
—
B/W
B/W
B
B
B
—
Function
Returns from an exception-handling routine.
(EAs) → CCR, (EAs) → EXR
Moves the memory operand contents or immediate data to CCR or
EXR. Although CCR and EXR are 8-bit registers, word-size transfers
are performed between them and memory. The upper 8 bits are valid.
CCR → (EAd), EXR → (EAd)
Transfers CCR or EXR contents to a general register or memory
operand. Although CCR and EXR are 8-bit registers, word-size
transfers are performed between them and memory. The upper 8 bits
are valid.
CCR ∧ #IMM → CCR, EXR ∧ #IMM → EXR
Logically ANDs the CCR or EXR contents with immediate data.
CCR ∨ #IMM → CCR, EXR ∨ #IMM → EXR
Logically ORs the CCR or EXR contents with immediate data.
CCR ⊕ #IMM → CCR, EXR ⊕ #IMM → EXR
Logically exclusive-ORs the CCR or EXR contents with immediate data.
PC + 2 → PC
Only increments the program counter.
Starts trap-instruction exception handling.
Causes a transition to a power-down state.
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