HD6412373R RENESAS [Renesas Technology Corp], HD6412373R Datasheet - Page 369
HD6412373R
Manufacturer Part Number
HD6412373R
Description
Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2300 Series
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet
1.HD6412373R.pdf
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Bit
5
Bit Name
DTME0
Initial Value
0
R/W
R/W
Description
Data Transfer Master Enable 0
Together with the DTE0 bit, this bit controls
enabling or disabling of data transfer on channel 0.
When both the DTME0 bit and DTE0 bit are set to
1, transfer is enabled for channel 0.
If channel 0 is in the middle of a burst mode
transfer when an NMI interrupt is generated, the
DTME0 bit is cleared, the transfer is interrupted,
and bus mastership passes to the CPU. When the
DTME0 bit is subsequently set to 1 again, the
interrupted transfer is resumed. In block transfer
mode, however, the DTME0 bit is not cleared by an
NMI interrupt, and transfer is not interrupted.
[Clearing conditions]
•
•
•
[Setting condition]
When 1 is written to DTME0 after reading DTME0 =
0
When initialization is performed
When NMI is input in burst mode
When 0 is written to the DTME0 bit
Rev.7.00 Mar. 18, 2009 page 301 of 1136
Section 7 DMA Controller (DMAC)
REJ09B0109-0700
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