HD6412373R RENESAS [Renesas Technology Corp], HD6412373R Datasheet - Page 877
HD6412373R
Manufacturer Part Number
HD6412373R
Description
Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2300 Series
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet
1.HD6412373R.pdf
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17.3.2
ADCSR controls A/D conversion operations.
Bit
7
6
5
4
Bit Name
ADF
ADIE
ADST
—
A/D Control/Status Register (ADCSR)
Initial Value
0
0
0
0
R/W
R/(W) *
R/W
R/W
—
Description
A/D End Flag
A status flag that indicates the end of A/D
conversion.
[Setting conditions]
•
•
[Clearing conditions]
•
•
A/D Interrupt Enable
A/D conversion end interrupt (ADI) request enabled
when 1 is set
A/D Start
Clearing this bit to 0 stops A/D conversion, and the
A/D converter enters wait state. When this bit is set
to 1 by software, TPU (trigger), TMR (trigger), or the
ADTRG pin, A/D conversion starts. This bit remains
set to 1 during A/D conversion. In single mode,
cleared to 0 automatically when conversion on the
specified channel ends. In scan mode, conversion
continues sequentially on the specified channels
until this bit is cleared to 0 by a reset, a transition to
hardware standby mode or software.
Reserved
This bit is always read as 0 and cannot be modified.
When A/D conversion ends in single mode
When A/D conversion ends on all specified
channels in scan mode
When 0 is written after reading ADF = 1
When the DTC or DMAC is activated by an ADI
interrupt and ADDR is read
Rev.7.00 Mar. 18, 2009 page 809 of 1136
Section 17 A/D Converter
REJ09B0109-0700
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