HD6417618 RENESAS [Renesas Technology Corp], HD6417618 Datasheet - Page 135

• Manufacturer Part Number: HD6417618
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7618 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Table 6.3
Notes: *
Item
Interrupt priority decision
and comparison with mask
bits in SR
Wait for completion of
sequence currently being
executed by CPU
Time from start of interrupt
exception handling until
fetch of first instruction of
exception handling routine
starts
Interrupt
response
time
In the case that m1 = m2 = m3 = m4 = 1 × Icyc.
m1 to m4 are the number of cycles needed for the following memory accesses.
m1: SR save (longword write)
m2: PC save (longword write)
m3: Vector address read (longword read)
m4: Fetch first instruction of interrupt service routine
Interrupt Response Time
Minimum*:
Maximum:
Total:
9 × Icyc + 2 × Pcyc
16 × Icyc +
NMI, H-UDI
1 × Icyc + 2 × Pcyc
X (≥ 0)
8 × Icyc + m1 + m2
+ m3
+ m1 + m2 + m3
+ X
12 × Icyc +
2 × Pcyc
2 × Pcyc + 2 ×
(m1 + m2 + m3) +
m4
Number of Cycles
IRQ, Peripheral
Modules
1 × Icyc + 3 × Pcyc
X (≥ 0)
8 × Icyc + m1 + m2
+ m3
9 × Icyc + 3 × Pcyc
+ m1 + m2 + m3
+ X
12 × Icyc +
3 × Pcyc
16 × Icyc +
3 × Pcyc + 2 ×
(m1 + m2 + m3) +
m4
Rev. 6.00 Jun. 12, 2007 Page 103 of 610
Section 6 Interrupt Controller (INTC)
Remarks
The longest sequence
is for interrupt or
address-error
exception handling (X =
7 × Icyc + m1 + m2
+ m3 + m4). If an
interrupt-masking
instruction follows,
however, the time may
be even longer.
Performs the saving
PC and SR, and vector
address fetch.
SR, PC, and vector
table are all in on-chip
RAM, or cache hit
occurs (in write back
mode).
REJ09B0131-0600