HD6417618 RENESAS [Renesas Technology Corp], HD6417618 Datasheet - Page 287

• Manufacturer Part Number: HD6417618
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7618 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

11.4.5
The EtherC has a Magic Packet detection function. This function provides a Wake-On-LAN
(WOL) facility that activates various peripheral devices connected to a LAN from the host device
or other source. This makes it possible to construct a system in which a peripheral device receives
a Magic Packet sent from the host device or other source, and activates itself. When the Magic
Packet is detected, data is stored in the FIFO of the E-DMAC by the broadcast packet that has
received data previously and the EtherC is notified of the receiving status. To return to normal
operation from the interrupt processing, initialize the EtherC and E-DMAC by using the SWR bit
in the E-DMAC mode register (EDMR).
With a Magic Packet, reception is performed regardless of the destination address. As a result, this
function is valid, and the WOL pin enabled, only in the case of a match with the destination
address specified by the format in the Magic Packet. Further information on Magic Packets can be
found in the technical documentation published by AMD Corporation.
The procedure for using the WOL function with this LSI is as follows.
1. Disable interrupt source output by means of the various interrupt enable/mask registers.
2. Set the Magic Packet detection enable bit (MPDE) in the EtherC mode register (ECMR).
3. Set the Magic Packet detection interrupt enable bit (MPDIP) in the EtherC interrupt enable
4. If necessary, set the CPU operating mode to sleep mode or set supporting functions to module
5. When a Magic Packet is detected, an interrupt is sent to the CPU. The WOL pin notifies
register (ECSIPR) to the enable setting.
standby mode.
peripheral LSIs that the Magic Packet has been detected.
Figure 11.6 (4) Independent Bus Release Flowchart (IDLE in Write in Figure 11.5)
Magic Packet Detection
(1)
Write to PHY interface
register
MMD = 0
MDC = 0
MDC
MDO
Rev. 6.00 Jun. 12, 2007 Page 255 of 610
Section 11 Ethernet Controller (EtherC)
Independent bus release
timing relationship
(1)
REJ09B0131-0600