HD6417729 HITACHI [Hitachi Semiconductor], HD6417729 Datasheet - Page 222

• Manufacturer Part Number: HD6417729
• Description: Hitachi Microcomputer Development Environment System
• Manufacturer: HITACHI [Hitachi Semiconductor]

Rev. 2.0, 01/01, page 198 of 216
Environment:
When a one-byte memory is read from the command-line window, the stopping time will be
about 47 ms.
Interrupt
When the BLMSK bit in the ICR1 register is 1, the NMI interrupt is accepted during break and
the program is executed from the NMI interrupt vector. If the program cannot return normally
from the NMI interrupt routine or the value in the general-purpose register is not guaranteed, a
communication timeout error will occur.
Memory Access during User Program Break
The emulator can download the program for the flash memory area. Other memory write
operations are enabled for the RAM area. Therefore, an operation such as memory write,
BREAKPOINT, or user program download should be set only for the RAM area. When the
memory area can be written by the MMU, do not perform memory write, BREAKPOINT, or
downloading.
Cache Operation during User Program Break
When cache is enabled, the emulator accesses the memory by the following methods:
Therefore, when memory read or write is performed during user program break, the cache
state will be changed.
At memory write: Writes through the cache, then writes to the memory.
At memory read: Does not change the cache write mode that has been set.
Host computer: 500 MHz (Pentium
SH7729: 50 MHz (CPU clock)
JTAG clock: 15 MHz
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