HD6433045 HITACHI [Hitachi Semiconductor], HD6433045 Datasheet - Page 106

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HD6433045

Manufacturer Part Number
HD6433045
Description
Hitachi Single-Chip Microcomputer
Manufacturer
HITACHI [Hitachi Semiconductor]
Datasheet

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5.2.3 IRQ Status Register (ISR)
ISR is an 8-bit readable/writable register that indicates the status of IRQ
requests.
ISR is initialized to H'00 by a reset and in hardware standby mode.
Bits 7 and 6—Reserved: Read-only bits, always read as 0.
Bits 5 to 0—IRQ
IRQ
Bits 5 to 0
IRQ5F to IRQ0F
0
1
Note: n = 5 to 0
Bit
Initial value
Read/Write
Note:
5
to IRQ
*
Only 0 can be written, to clear flags.
0
interrupt requests.
5
Reserved bits
to IRQ
Description
[Clearing conditions]
0 is written in IRQnF after reading the IRQnF flag when IRQnF = 1.
IRQnSC = 0, IRQn input is high, and interrupt exception handling is carried out.
IRQnSC = 1 and IRQn interrupt exception handling is carried out.
[Setting conditions]
IRQnSC = 0 and IRQn input is low.
IRQnSC = 1 and IRQn input changes from high to low.
7
0
0
Flags (IRQ
6
0
IRQ5F
R/(W) *
5
5
0
F to IRQ
92
IRQ4F
R/(W) *
0
4
0
F): These bits indicate the status of
IRQ to IRQ flags
These bits indicate IRQ to IRQ
interrupt request status
IRQ3F
R/(W) *
3
0
5
IRQ2F
R/(W) *
0
2
0
0
to IRQ
IRQ1F
R/(W) *
5
5
1
0
interrupt
(Initial value)
IRQ0F
R/(W) *
0
0
0

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