HD6433045 HITACHI [Hitachi Semiconductor], HD6433045 Datasheet - Page 137

• Manufacturer Part Number: HD6433045
• Description: Hitachi Single-Chip Microcomputer
• Manufacturer: HITACHI [Hitachi Semiconductor]

6.3.2 Chip Select Signals
For each of areas 0 to 7, the H8/3048 Series can output a chip select signal (CS
low to indicate when the area is selected. Figure 6-3 shows the output timing of a CS
(n = 0 to 7).
Output of CS
(DDR) of the corresponding port.
In the expanded modes with on-chip ROM disabled, a reset leaves pin CS
pins CS
DDR bits must be set to 1. In the expanded modes with on-chip ROM enabled, a reset leaves pins
CS
bits must be set to 1. For details see section 9, I/O Ports.
Output of CS
register (CSCR). A reset leaves pins CS
CS
When the on-chip ROM, on-chip RAM, and on-chip registers are accessed, CS
high. The CS
signals for SRAM and other devices.
Address
bus
CS
ø
0
4
to CS
to CS
n
1
to CS
3
7
, the corresponding CSCR bits must be set to 1. For details see section 9, I/O Ports.
in the input state. To output chip select signals CS
n
0
4
signals are decoded from the address signals. They can be used as chip select
3
to CS
to CS
in the input state. To output chip select signals CS
3
7
: Output of CS
: Output of CS
Figure 6-3 CS
External address in area n
0
4
to CS
to CS
4
to CS
n
Output Timing (n = 0 to 7)
3
7
is enabled or disabled in the data direction register
is enabled or disabled in the chip select control
7
123
in the input state. To output chip select signals
0
to CS
1
to CS
3
, the corresponding DDR
0
3
, the corresponding
in the output state and
0
0
and CS
to CS
n
7
signal
) that goes
7
remain