HD6433045 HITACHI [Hitachi Semiconductor], HD6433045 Datasheet - Page 246

• Manufacturer Part Number: HD6433045
• Description: Hitachi Single-Chip Microcomputer
• Manufacturer: HITACHI [Hitachi Semiconductor]

8.4.10 External Bus Requests, Refresh Controller, and DMAC
During a DMA transfer, if the bus right is requested by an external bus request signal (BREQ) or
by the refresh controller, the DMAC releases the bus after completing the transfer of the current
byte or word. If there is a transfer request at this point, the DMAC requests the bus right again.
Figure 8-20 shows an example of the timing of insertion of a refresh cycle during a burst transfer
on channel 0.
ø
Address
bus
RD
HWR
LWR
ø
Address
bus
RD
HWR LWR
,
,
DMAC cycle
(channel 1)
T
1
Figure 8-20 Bus Timing of Refresh Controller and DMAC
T
1
Figure 8-19 Timing of Multiple-Channel Operations
T
2
DMAC cycle (channel 0)
T
2
T
1
T
1
T
CPU
cycle
2
T
2
T
1
T
d
T
2
T
1
DMAC cycle
(channel 0A)
T
1
232
T
2
T
2
T
T
1
Refresh
cycle
1
T
T
2
2
T
T
1
d
CPU
cycle
T
T
2
DMAC cycle (channel 0)
1
T
T
d
2
T
T
1
DMAC cycle
(channel 1)
1
T
T
2
2
T
T
1
1
T
T
2
2