HD6433045 HITACHI [Hitachi Semiconductor], HD6433045 Datasheet - Page 292

• Manufacturer Part Number: HD6433045
• Description: Hitachi Single-Chip Microcomputer
• Manufacturer: HITACHI [Hitachi Semiconductor]

Port A Data Register (PADR): PADR is an 8-bit readable/writable register that stores output data
for pins PA
corresponding PADR bit is returned. When a bit in PADDR is cleared to 0, if port A is read the
corresponding pin level is read.
PADR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode it
retains its previous setting.
9.11.3 Pin Functions
Table 9-19 describes the selection of pin functions.
Table 9-19 Port A Pin Functions
Pin
PA
TIOCB
7
/TP
2
Bit
Initial value
Read/Write
7
/A
/
20
7
to PA
Pin Functions and Selection Method
The mode setting, ITU channel 2 settings (bit PWM2 in TMDR and bits IOB2 to
IOB0 in TIOR2), bit NDER7 in NDERA, and bit PA
function as follows
Note: * TIOCB
Mode
ITU channel 2
settings
PA
NDER7
Pin function
ITU channel 2
settings
IOB2
IOB1
IOB0
0
7
. When a bit in PADDR is set to 1, if port A is read the value of the
DDR
R/W
PA
0
7
7
2
input when IOB2 = 1 and PWM2 = 0.
R/W
PA
0
6
6
(1) in table below
(2)
0
0
TIOCB
R/W
PA
0
5
5
—
—
0
2
Port A data 7 to 0
These bits store data for port A pins
279
output
0
1
PA
R/W
0
4
(1)
4
—
1, 2, 5, 7
1
PA
R/W
0
3
3
input
PA
—
7
0
DDR in PADDR select the pin
(2) in table below
7
R/W
PA
TIOCB
0
2
2
output
PA
(2)
—
—
0
1
1
2
7
input*
PA
R/W
0
1
1
output
TP
1
1
7
PA
R/W
0
0
0
3, 4, 6
output
A
—
—
—
20