HD6433045 HITACHI [Hitachi Semiconductor], HD6433045 Datasheet - Page 518

• Manufacturer Part Number: HD6433045
• Description: Hitachi Single-Chip Microcomputer
• Manufacturer: HITACHI [Hitachi Semiconductor]

14.3.4 Register Settings
Table 14-3 shows a bit map of the registers used in the smart card interface. Bits indicated as 0 or
1 should always be set to the indicated value. The settings of the other bits will be described in
this section.
Table 14-3 Register Settings in Smart Card Interface
Register
SMR
BRR
SCR
TDR
SSR
RDR
SCMR
Notes: — Unused bit.
Serial Mode Register (SMR) Settings: In regular smart card interface mode, set the GM bit at 0.
In regular smart card mode, clear the GM bit to 0. In GSM mode, set the GM bit to 1. Clear the
O/E bit to 0 if the smart card uses the direct convention. Set the O/E bit to 1 if the smart card uses
the inverse convention. Bits CKS1 and CKS0 select the clock source of the built-in baud rate
generator. See section 14.3.5, Clock.
Bit Rate Register (BRR) Settings: This register sets the bit rate. Equations for calculating the
setting are given in section 14.3.5, Clock.
Serial Control Register (SCR): The TIE, RIE, TE, and RE bits have their normal serial
communication functions. For details, see section 13, Serial Communication Interface. The CKE1
and CKE0 bits select clock output. When the GM bit of the SMR is cleared to 0, to disable clock
output, clear this bit to 00. To enable clock output, set this bit to 01. When the GM bit of the SMR
is set to 1, clock output is enabled. Clock output is fixed at high or low.
Smart Card Mode Register (SCMR): If the smart card follows the direct convention, clear the
SDIR and SINV bits to 0. If the smart card follows the indirect convention, set the SDIR and
SINV bits to 1. To use the smart card interface, set the SMIF bit to 1.
1. Lower 16 bits of the address.
2. When the GM of the SMR is set at 0, be sure the CKE1 bit is 0.
Address*
H'FFB0
H'FFB1
H'FFB2
H'FFB3
H'FFB4
H'FFB5
H'FFB6
1
Bit 7
GM
BRR7
TIE
TDR7
TDRE
RDR7
—
Bit 6
0
BRR6
RIE
TDR6
RDRF
RDR6
—
Bit 5
1
BRR5
TE
TDR5
ORER
RDR5
—
508
Bit 4
O/E
BRR4
RE
TDR4
ERS
RDR4
—
Bit 3
1
BRR3
0
TDR3
PER
RDR3
SDIR
Bit 2
0
BRR2
0
TDR2
TEND
RDR2
SINV
Bit 1
CKS1
BRR1
CKE1*
TDR1
0
RDR1
—
2
Bit 0
CKS0
BRR0
CKE0
TDR0
0
RDR0
SMIF