HD6433045 HITACHI [Hitachi Semiconductor], HD6433045 Datasheet - Page 519

• Manufacturer Part Number: HD6433045
• Description: Hitachi Single-Chip Microcomputer
• Manufacturer: HITACHI [Hitachi Semiconductor]

The register settings and examples of starting character waveforms are shown below for two smart
cards, one following the direct convention and one the inverse convention.
Direct convention (SDIR = SINV = O/E = 0)
(Z)
A
Z
Z
A
Z
Z
Z
A
A
Z
(Z)
State
Ds
D0
D1
D2
D3
D4
D5
D6
D7
Dp
In the direct convention, state Z corresponds to logic level 1, and state A to logic level 0.
Characters are transmitted and received LSB-first. In the example above the first character data is
H'3B. The parity bit is 1, following the even parity rule designated for smart cards.
Inverse convention (SDIR = SINV = O/E = 1)
(Z)
A
Z
Z
A
A
A
A
A
A
Z
(Z)
State
Ds
D7
D6
D5
D4
D3
D2
D1
D0
Dp
In the inverse convention, state A corresponds to the logic level 1, and state Z to the logic level 0.
Characters are transmitted and received MSB-first. In the example above the first character data is
H'3F. Following the even parity rule designated for smart cards, the parity bit logic level is 0,
corresponding to state Z.
In the H8/3048 Series, the SINV bit inverts only the data bits D7 to D0. The parity bit is not
inverted, so the O/E bit in SMR must be set to odd parity mode. This applies in both transmitting
and receiving.
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