HD6433045 HITACHI [Hitachi Semiconductor], HD6433045 Datasheet - Page 617

• Manufacturer Part Number: HD6433045
• Description: Hitachi Single-Chip Microcomputer
• Manufacturer: HITACHI [Hitachi Semiconductor]

Hardware Protection: Suspends or disables the programming and erasing of flash memory, and
resets the flash memory control register (FLMCR) and erase block registers (EBR1 and EBR2).
The error-protect function permits the P and E bits to be set, but prevents transitions to program
mode and erase mode. Details of hardware protection are as follows.
Protection
Programing
voltage (V
protect
Reset and
standby
protect
Error protect
Notes: 1. Program-verify, erase-verify, and prewrite-verify modes.
Error Protect: This protection mode is entered if one of the error conditions that set the FLER bit
in RAMCR is detected while flash memory is being programmed or erased (while the P bit or E
bit is set in FLMCR). These conditions can occur if microcontroller operations do not follow the
programming or erasing algorithm. Error protect is a flash-memory state. It does not affect other
microcontroller operations.
In this state the settings of the flash memory control register (FLMCR) and erase block registers
(EBR1 and EBR2) are preserved,* but program mode or erase mode is terminated as soon as the
error is detected. While the FLER bit is set, it is not possible to enter program mode or erase
mode, even by setting the P bit or E bit in FLMCR again. The PV and EV bits in FLMCR remain
valid, however. Transitions to verify modes are possible in the error-protect state.
2. All blocks are erase-disabled. It is not possible to specify individual blocks.
3. For details, see section 18.10, Flash Memory Programming and Erasing Precautions.
PP
)
Description
When V
and EBR2 are initialized, disabling
programming and erasing. To obtain this
protection, V
When a reset occurs (including a watchdog
timer reset) or standby mode is entered,
FLMCR, EBR1, and EBR2 are initialized,
disabling programming and erasing.
Note that
reset unless the RES pin is held low for
at least 20 ms at power-up (to enable
the oscillator to settle), or at least 10
system clock cycles (
If an operational error is detected during
programming or erasing of flash memory
(FLER = 1), the FLMCR, EBR1, and EBR2
settings are preserved, but programming
or erasing is aborted immediately.
This type of protection can be cleared
only by a reset or hardware standby.
PP
RES input does not ensure a
is not applied, FLMCR, EBR1,
PP
should not exceed V
ø
) during operation.
608
CC
.*
3
Program
Disabled
Disabled
Disabled
Function
Erase
Disabled*
Disabled*
Disabled*
2
2
2
Verify*
Disabled
Disabled
Enabled
1