HD6433045 HITACHI [Hitachi Semiconductor], HD6433045 Datasheet - Page 76

• Manufacturer Part Number: HD6433045
• Description: Hitachi Single-Chip Microcomputer
• Manufacturer: HITACHI [Hitachi Semiconductor]

3.4.7 Mode 7
This mode operates using the on-chip ROM, RAM, and registers. All I/O ports are available. Mode 7
supports a 1-Mbyte address space.
3.5 Pin Functions in Each Operating Mode
The pin functions of ports 1 to 5 and port A vary depending on the operating mode. Table 3-3
indicates their functions in each operating mode.
Table 3-3 Pin Functions in Each Mode
Port
Port 1
Port 2
Port 3
Port 4
Port 5
Port A
Notes: 1. Initial state. The bus mode can be switched by settings in ABWCR. These pins function
3.6 Memory Map in Each Operating Mode
Figure 3-1 shows a memory map of the H8/3048. Figure 3-2 shows a memory map of the
H8/3047. Figure 3-3 shows a memory map of the H8/3044. Figure 3-4 shows a memory map of
the H8/3045. The address space is divided into eight areas.
The initial bus mode differs between modes 1 and 2, and also between modes 3 and 4.
The address locations of the on-chip RAM and on-chip registers differ between the 1-Mbyte modes
(modes 1, 2, 5, and 7) and 16-Mbyte modes (modes 3, 4, and 6). The address range specifiable by
the CPU in the 8- and 16-bit absolute addressing modes (@aa:8 and @aa:16) also differs.
Mode 1
A
A
D
P4
A
PA
7
15
19
2. Initial state. These pins become address output pins when the corresponding bits in the
3. Initial state. A
15
7
to A
7
to A
to A
to D
to P4
to PA
as P4
data direction registers (P1DDR, P2DDR, P5DDR) are set to 1.
A
0
21
8
16
8
0
4
*1
output by writing 0 in bits 7 to 5 of BRCR.
7
to P4
Mode 2
A
A
D
D
A
PA
7
15
19
15
7
7
to A
to D
to A
to A
to D
to PA
0
0
20
0
8
16
in 8-bit bus mode, and as D
8
*1
4
is always an address output pin. PA
Mode 3
A
A
D
P4
A
PA
7
15
19
15
7
to A
7
to A
to A
to D
to P4
to PA
0
8
16
8
0
5
*1
*3
, A
20
Mode 4
A
A
D
D
A
PA
7
15
19
15
7
61
7
to A
to D
to A
to A
to D
to PA
0
0
8
16
8
*1
7
5
*3
to D
, A
20
0
in 16-bit bus mode.
Mode 5
P1
P2
D
P4
P5
PA
15
7
7
7
7
3
7
to PA
to D
to P1
to P2
to P4
to P5
to PA
8
0
0
0
0
4
*2
*2
*1
*2
5
are switched over to A
Mode 6
P1
P2
D
P4
P5
PA
15
7
7
7
3
7
to D
to P1
to P2
to P4
to P5
to PA
8
0
0
0
0
5
*2
*2
*1
*2
, A
20
*3
Mode 7
P1
P2
P3
P4
P5
PA
7
7
7
7
3
7
to P1
to P2
to P3
to P4
to P5
to PA
23
0
0
0
0
0
4
to