HD6433308 HITACHI [Hitachi Semiconductor], HD6433308 Datasheet - Page 15

• Manufacturer Part Number: HD6433308
• Description: Hitachi Single-Chip MicroComputer
• Manufacturer: HITACHI [Hitachi Semiconductor]

Figure 5-2
Figure 5-3
Figure 5-4
Figure 5-5
Figure 5-6
Figure 5-7
Figure 5-8
Figure 5-9
Figure 5-10
Figure 5-11
Figure 5-12
Figure 5-13
Figure 5-14
Figure 5-15
Figure 5-16
Figure 5-17
Figure 5-18
Figure 5-19
Figure 5-20
Figure 5-21
Figure 5-22
Figure 5-23
Figure 5-24
Figure 5-25
Figure 6-1
Figure 6-2
Figure 6-3
Figure 6-4 (a) Write Access to FRC (When CPU Writes H'AA55) ............................................. 138
Figure 6-4 (b) Read Access to FRC (When FRC Contains H'AA55) .......................................... 139
Figure 6-5
Figure 6-6
Figure 6-7
Figure 6-8
Figure 6-9
Figure 6-10
Figure 6-11
Figure 6-12
Port 2 Schematic Diagram..................................................................................... 84
Port 3 Schematic Diagram..................................................................................... 87
Port 4 Schematic Diagram (Pins P4
Port 4 Schematic Diagram (Pins P4
Port 5 Schematic Diagram (Pin P5
Port 5 Schematic Diagram (Pin P5
Port 5 Schematic Diagram (Pin P5
Port 6 Schematic Diagram (Pins P6
Port 6 Schematic Diagram (Pin P6
Port 6 Schematic Diagram (Pin P6
Port 6 Schematic Diagram (Pin P6
Port 7 Schematic Diagram..................................................................................... 103
Port 8 Schematic Diagram (Pin P8
Port 8 Schematic Diagram (Pin P8
Port 8 Schematic Diagram (Pins P8
Port 8 Schematic Diagram (Pin P8
Port 8 Schematic Diagram (Pin P8
Port 8 Schematic Diagram (Pin P8
Port 9 Schematic Diagram (Pin P9
Port 9 Schematic Diagram (Pins P9
Port 9 Schematic Diagram (Pins P9
Port 9 Schematic Diagram (Pin P9
Port 9 Schematic Diagram (Pin P9
Port 9 Schematic Diagram (Pin P9
Block Diagram of 16-Bit Free-Running Timer..................................................... 124
Input Capture Buffering ........................................................................................ 128
Minimum Input Capture Pulse Width ................................................................... 128
Increment Timing for Internal Clock Source ........................................................ 140
Increment Timing for External Clock Source ....................................................... 140
Minimum External Clock Pulse Width ................................................................. 140
Setting of Output Compare Flags.......................................................................... 141
Clearing of Output Compare Flag......................................................................... 141
Timing of Output Compare A ............................................................................... 142
Clearing of FRC by Compare-Match A ................................................................ 142
Input Capture Timing (Usual Case) ...................................................................... 143
xii
0
1
2
1
6
7
0
1
4
5
6
0
5
6
7
)..................................................................... 94
)..................................................................... 95
)..................................................................... 96
)..................................................................... 100
)..................................................................... 101
)..................................................................... 102
)..................................................................... 108
)..................................................................... 109
)..................................................................... 111
)..................................................................... 112
)..................................................................... 113
)..................................................................... 117
)..................................................................... 120
)..................................................................... 121
)..................................................................... 122
0
1
0
2
1
3
, P4
, P4
, P6
and P8
to P9
and P9
2
4
2
, P4
, P4
, P6
2
) ........................................................ 118
3
4
)...................................................... 110
)...................................................... 119
3
6
3
, and P4
, and P4
, P6
4
, and P6
5
7
) ..................................... 90
) ..................................... 91
5
).............................. 99