HD6433308 HITACHI [Hitachi Semiconductor], HD6433308 Datasheet - Page 250

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HD6433308

Manufacturer Part Number
HD6433308
Description
Hitachi Single-Chip MicroComputer
Manufacturer
HITACHI [Hitachi Semiconductor]
Datasheet

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Table 12-1. System Control Register
Name
System control register
Bit
Initial value
Read/Write
The only bit in the system control register that concerns the on-chip RAM is the RAME bit. See
section 2.4.2, "System Control Register" for the other bits.
Bit 0 – RAM Enable (RAME): This bit enables or disables the on-chip RAM.
The RAME bit is initialized to “1” on the rising edge of the RES signal, so a reset enables the on-
chip RAM. The RAME bit is not initialized in the software standby mode.
Bit 7
RAME
12.4 Operation
12.4.1 Expanded Modes (Modes 1 and 2)
If the RAME bit is set to “1,” accesses to addresses H’FD80 to H’FF7F are directed to the on-chip
RAM. If the RAME bit is cleared to “0,” accesses to addresses H’FD80 to H’FF7F are directed to
the external data bus.
12.4.2 Single-Chip Mode (Mode 3)
If the RAME bit is set to “1,” accesses to addresses H’FD80 to H’FF7F are directed to the on-chip
RAM.
If the RAME bit is cleared to “0,” the on-chip RAM data cannot be accessed. Attempted write
access has no effect. Attempted read access always results in H’FF data being read.
0
1
Description
On-chip RAM is disabled.
On-chip RAM is enabled.
SSBY
R/W
7
0
STS2
R/W
Abbreviation
SYSCR
6
0
STS1
R/W
5
0
R/W
R/W
STS0
240
R/W
4
0
Initial value
H’09
3
1
NMIEG DPME
R/W
2
0
Address
H’FFC4
R/W
1
0
(Initial value)
RAME
R/W
0
1

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