HD6433308 HITACHI [Hitachi Semiconductor], HD6433308 Datasheet - Page 318

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HD6433308

Manufacturer Part Number
HD6433308
Description
Hitachi Single-Chip MicroComputer
Manufacturer
HITACHI [Hitachi Semiconductor]
Datasheet

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TCSR—Timer Control/Status Register
Bit
Initial value
Read/Write R/(W)* R/(W)*
* Software can write a "0" in bits 7 to 1 to clear the flags, but cannot write a "1" in these bits
Input Capture Flag A
0 Cleared when CPU reads ICFA = “1”, then writes “0” in ICFA.
1 Set when FTIA input causes FRC to be copied to ICRA.
Input Capture Flag B
1 Set when FTIB input causes FRC to be copied to ICRB.
0 Cleared when CPU reads ICFB = “1”, then writes “0” in ICFB.
Input Capture Flag C
0 Cleared when CPU reads ICFC = “1”, then writes “0” in ICFC.
1 Set by FTIC input.
ICFA
7
0
Input Capture Flag D
0 Cleared when CPU reads ICFD = “1”, then writes “0” in ICFD.
1 Set by FTID input.
ICFB
0
6
1 Set when FRC = OCRA.
Output Compare Flag A
0 Cleared when CPU reads OCFA = “1”, then writes “0” in OCFA.
Output Compare Flag B
0 Cleared when CPU reads OCFB = “1”, then writes “0” in OCFB.
1 Set when FRC = OCRB.
R/(W)*
ICFC
Timer Overflow Flag
0 Cleared when CPU reads OVF = “1,” then writes “0” in OVF.
1 Set when FRC changes from H’FFFF to H’0000.
0
5
R/(W)* R/(W)* R/(W)* R/(W)*
ICFD
0
4
310
Counter Clear A
0 FRC count is not cleared.
1 FRC count is cleared by compare-match A.
OCFA
3
0
H’FF91
OCFB
2
0
OVF
1
0
FRT
CCLRA
R/W
0
0

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