HD6433308 HITACHI [Hitachi Semiconductor], HD6433308 Datasheet - Page 68

• Manufacturer Part Number: HD6433308
• Description: Hitachi Single-Chip MicroComputer
• Manufacturer: HITACHI [Hitachi Semiconductor]

3.6.1 Program Execution State
In this state the CPU executes program instructions in sequence. The main program, subroutines,
and interrupt-handling routines are all executed in this state.
3.6.2 Exception-Handling State
The exception-handling state is a transient state that occurs when the CPU is reset or accepts an
interrupt. In this state the CPU carries out a hardware-controlled sequence that prepares it to
execute a user-coded exception-handling routine.
In the hardware exception-handling sequence the CPU does the following:
See section 4, “Exception Handling,” for further information on the exception-handling state.
(1)
(2)
(3)
(4)
Notes:
1. A transition to the reset state occurs when RES goes Low, except when the chip is in the hardware standby mode.
2. A transition from any state to the hardware standby mode occurs when STBY goes Low.
Saves the program counter and condition code register to the stack (except in the case of a
reset).
Sets the interrupt mask (I) bit in the condition code register to “1.”
Fetches the start address of the exception-handling routine from the vector table.
Branches to that address, returning to the program execution state.
RES = 1
Exception -
handling state
Reset state
Exception
Exception-
handling
handing
request
request
NMI or IRQ
to IRQ
STBY=1 or RES=0
Figure 3-12. State Transitions
Exception
handing
Interrupt request
Program
execution state
7
0
52
SLEEP
instruction
Power-down state
Sleep mode
Software
standby mode
Hardware
standby mode
SLEEP instruction
with SSBY bit set