HD6433308 HITACHI [Hitachi Semiconductor], HD6433308 Datasheet - Page 80

• Manufacturer Part Number: HD6433308
• Description: Hitachi Single-Chip MicroComputer
• Manufacturer: HITACHI [Hitachi Semiconductor]

Figure 4-3 shows a block diagram of the interrupt controller. Figure 4-4 is a flowchart showing the
operation of the interrupt controller and the sequence by which an interrupt is accepted. This
sequence is outlined below.
(1) The interrupt controller receives an interrupt request signal. Interrupt request signals can be
(2) When notified of an interrupt, the interrupt controller scans the interrupt signals in priority
(3) The interrupt controller accepts the interrupt if it is an NMI, or if it is another interrupt and the
(4) When an interrupt is accepted, after completion of the current instruction, the CPU pushes first
(5) The CPU sets the I bit in the CCR to “1,” masking all further interrupts except NMI during the
(6) The CPU generates the vector address of the interrupt and loads the word at this address into
(7) Execution of the software interrupt-handling routine starts from the address now in the pro-
(8) On the return from the interrupt-handling routine (RTE instruction), the CCR and PC are
The timing of this sequence is shown in Figure 4-5 for the case in which the program and vector
table are in on-chip ROM and the stack is in on-chip RAM.
order and selects the one with the highest priority. (See table 4-2 for the priority order.) Other
requested interrupts remain pending.
I bit in the CCR is cleared to “0.” If the interrupt is not an NMI and the I bit is set to “1,” the
interrupt is held pending.
the PC then the CCR onto the stack. The stacked PC indicates the address of the first
instruction that will be executed after the return. The stack pointer (R7) must indicate an even
address. See section 4.2.5, “Note on Stack Handling” for details.
interrupt-handling routine.
the program counter.
gram counter.
popped from the stack and execution of the interrupted program resumes.
generated by:
—
—
—
All interrupts except NMI have enable bits. The interrupt can be requested only when its
enable bit is set to "1."
A High-to-Low (or Low-to-High) transition of the NMI signal
A Low input (or High-to-Low transition) of one of the IRQ
An on-chip supporting module
65
0
to IRQ
7
signals