HD6433308 HITACHI [Hitachi Semiconductor], HD6433308 Datasheet - Page 87

• Manufacturer Part Number: HD6433308
• Description: Hitachi Single-Chip MicroComputer
• Manufacturer: HITACHI [Hitachi Semiconductor]

registers of the on-chip supporting modules. The interrupt controller does not reset these flag bits
when accepting the interrupt. The flag bit must be reset by the software interrupt-handling routine.
To reset an interrupt flag, software must read the relevant bit or register, then clear the flag bit to
“0.” The flag bit cannot be cleared unless it is first read. The following is a coding example that
clears the A/D interrupt flag (ADF bit) in the A/D control/status register.
Note: When disabling internal interrupts, note the following points.
1. Set the interrupt mask (I) to "1" before disabling an internal interrupt (an interrupt from an on-
2. If an instruction that disables an internal interrupt is executed while the interrupt mask (I) is
Example: The following coding disables the output compare A interrupt from the free-running
timer module in the H8/330 by clearing the OCIAE bit. The I bit is first set to "1."
ORC
BCLR
ANDC
Note: Interrupt requests are not detected immediately after the ANDC, ORC, XORC, and LDC
instructions.
For the priority order of these interrupts, see table 4-2.
4.2.4 Interrupt Response Time
Table 4-4 indicates the time that elapses from an interrupt request signal until the first instruction of
the software interrupt-handling routine is executed. Since the H8/330 accesses its on-chip memory
16 bits at a time, very fast interrupt service can be obtained by placing interrupt-handling routines
in on-chip ROM and the stack in on-chip RAM.
chip supporting module) or clearing an interrupt flag.
cleared to "0", and the interrupt is requested during execution of the instruction, the CPU
resolves this conflict as follows:
If one or more other interrupts are also requested, the other interrupt with the highest priority
is serviced.
If no other interrupt is requested, the CPU branches to the reset address.
#80, CCR
#3, @TIER
#7F, CCR
; Set I bit
; Disable output compare A interrupt
; Clear I bit
BCLR #7, @H’FFE8
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