HD6433308 HITACHI [Hitachi Semiconductor], HD6433308 Datasheet - Page 90

• Manufacturer Part Number: HD6433308
• Description: Hitachi Single-Chip MicroComputer
• Manufacturer: HITACHI [Hitachi Semiconductor]

4.2.6 Deferring of Interrupts
As noted previously, no interrupt is accepted immediately after a reset. System control instructions
that rewrite the CCR have a similar effect. Interrupts requests received during one of these
instructions are deferred until at least one more instruction has been executed.
The instructions that defer interrupts in this way are XORC, ORC, ANDC, and LDC. At the
completion of these instructions the interrupt controller does not check the interrupt signals. The
CPU therefore always proceeds to the next instruction. (And if the next instruction is one of these
four, the CPU also proceeds to the next instruction after that.) The interrupt-handling sequence
starts after the next instruction that is not one of these four has been executed. Figure 4-8 shows an
example.
SP
H'FFCF set in SP
PC :
PC :
SP :
R1 :
Figure 4-7. Example of Damage Caused by Setting an Odd Address in R7
H
L
L
Lower byte of program counter
Stack pointer
Upper byte of program counter
General register
BSR instruction
SP
PC is improperly stored
beyond top of stack
PC
PC
75
H
L
MOV.B R1L, @–R7
SP
PC is lost
PC
R1
H
L
L
H'FFCC
H'FFCD
H'FFCF