HD6475328-CP10 HITACHI [Hitachi Semiconductor], HD6475328-CP10 Datasheet - Page 100
HD6475328-CP10
Manufacturer Part Number
HD6475328-CP10
Description
original Hitachi CMOS microcomputer unit (MCU)
Manufacturer
HITACHI [Hitachi Semiconductor]
Datasheet
1.HD6475328-CP10.pdf
(459 pages)
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4.1 Overview
4.1.1 Types of Exception Handling and Their Priority
As indicated in table 4-1 (a) and (b), exception handling can be initiated by a reset, address error,
trace, interrupt, or instruction. An instruction initiates exception handling if the instruction is an
invalid instruction, a trap instruction, or a DIVXU instruction with zero divisor. Exception
handling begins with a hardware exception-handling sequence which prepares for the execution of
a user-coded software exception-handling routine.
There is a priority order among the different types of exceptions, as shown in table 4-1 (a). If two
or more exceptions occur simultaneously, they are handled in their order of priority. An
instruction exception cannot occur simultaneously with other types of exceptions.
Table 4-1 (a) Exceptions and Their Priority
High
Low
Table 4-1 (b) Instruction Exceptions
Exception Type
Invalid instruction
Trap instruction
Zero divide
Exception
Type
Reset
Address error
Trace
Interrupt
Start of Exception-Handling Sequence
Attempted execution of instruction with undefined code
Started by execution of trap instruction
Attempted execution of DIVXU instruction with zero divisor
Section 4 Exception Handling
Source
External
Internal
Internal
External,
internal
Detection Timing
RES Low-to-High transition
Instruction fetch or data read/write
bus cycle
End of instruction execution, if
T = “1” in status register
End of instruction execution or end
of exception-handling sequence
81
Start of Exception-
Handling Sequence
Immediately
End of instruction
execution
End of instruction
execution
End of instruction
execution
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